ADE7566ASTZF8 Analog Devices Inc, ADE7566ASTZF8 Datasheet - Page 93

• Manufacturer Part Number: ADE7566ASTZF8
• Description: IC ENERGY METER MCU 8K 64LQFP
• Manufacturer: Analog Devices Inc

Specifications of ADE7566ASTZF8

• Applications: Energy Measurement
• Core Processor: 8052
• Program Memory Type: FLASH (8 kB)
• Controller Series: ADE75xx
• Ram Size: 512 x 8
• Interface: I²C, SPI, UART
• Number Of I /o: 20
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Ic Function: Single Phase Energy Measurement IC
• Supply Voltage Range: 3.13V To 3.46V, 2.4V To 3.7V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

INTERRUPT SYSTEM
The unique power management architecture of the ADE7116/
ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 includes
an operating mode (PSM2) where the 8052 MCU core is shut
down. Events can be configured to wake the 8052 MCU core
from the PSM2 operating mode. A distinction is drawn here
between events that can trigger the wake-up of the 8052 MCU
core and events that can trigger an interrupt when the MCU
core is active. Events that can wake the core are referred to as
wake-up events, whereas events that can interrupt the program
flow when the MCU is active are called interrupts. See the 3.3 V
Peripherals and Wake-Up Events section to learn more about
events that can wake the 8052 core from PSM2 mode.
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 provide 12 interrupt sources with three priority levels.
The power management interrupt is at the highest priority level.
The other two priority levels are configurable through the
interrupt priority SFR (IP, Address 0xB8) and the interrupt
enable and Priority 2 SFR (IEIP2, Address 0xA9).
STANDARD 8052 INTERRUPT ARCHITECTURE
The standard 8052 interrupt architecture includes two tiers of
interrupts, where some interrupts are assigned a high priority
and others are assigned a low priority.
Table 77. Interrupt SFRs
SFR
IE
IP
IEIP2
WDCON
Table 78. Interrupt Enable SFR (IE, Address 0xA8)
Bit
7
6
5
4
3
2
1
0
1
This feature is not available in the ADE7116.
Bit Address
0xAF
0xAE
0xAD
0xAC
0xAB
0xAA
0xA9
0xA8
Address
0xA8
0xB8
0xA9
0xC0
Figure 87. Standard 8052 Interrupt Priority Levels
HIGH
LOW
Mnemonic
EA
ETEMP
ET2
ES
ET1
EX1
ET0
EX0
Default
0x00
0x00
0xA0
0x10
1
PRIORITY 1
PRIORITY 0
Yes
Yes
No
Yes
Bit Addressable
Description
Enables all interrupt sources. Set by the user. Cleared by the user to disable all interrupt sources.
Enables the temperature ADC interrupt. Set by the user.
Enables the Timer 2 interrupt. Set by the user.
Enables the UART serial port interrupt. Set by the user.
Enables the Timer 1 interrupt. Set by the user.
Enables External Interrupt 1 (INT1). Set by the user.
Enables the Timer 0 interrupt. Set by the user.
Enables External Interrupt 0 (INT0). Set by the user.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Description
Interrupt enable (see Table 78).
Interrupt priority (see Table 79).
Interrupt enable and Priority 2 (see Table 80).
Watchdog timer (see Table 85 and the Writing to the Watchdog Timer SFR (WDCON,
Address 0xC0) section).
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A Priority 1 interrupt can interrupt the service routine of a
Priority 0 interrupt, and if two interrupts of different priorities
occur at the same time, the Priority 1 interrupt is serviced first.
An interrupt cannot be interrupted by another interrupt of the
same priority level. If two interrupts of the same priority level
occur simultaneously, a polling sequence is observed. See the
Interrupt Priority section.
INTERRUPT ARCHITECTURE
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 possess advanced power supply management
features. To ensure a fast response to time-critical power supply
issues, such as a loss of line power, the power supply manage-
ment interrupt should be able to interrupt any interrupt service
routine. To enable the user to have full use of the standard 8052
interrupt priority levels, an additional priority level is added for the
power supply management (PSM) interrupt. The PSM interrupt
is the only interrupt at this highest interrupt priority level.
See the Power Supply Management (PSM) Interrupt section for
more information on the PSM interrupt.
INTERRUPT REGISTERS
The control and configuration of the interrupt system are carried
out through four interrupt-related SFRs, discussed in this section.
Figure 88. Interrupt Architecture
HIGH
LOW
PRIORITY 1
PRIORITY 0
PSM