ADE7566ASTZF8 Analog Devices Inc, ADE7566ASTZF8 Datasheet - Page 95

• Manufacturer Part Number: ADE7566ASTZF8
• Description: IC ENERGY METER MCU 8K 64LQFP
• Manufacturer: Analog Devices Inc

Specifications of ADE7566ASTZF8

• Applications: Energy Measurement
• Core Processor: 8052
• Program Memory Type: FLASH (8 kB)
• Controller Series: ADE75xx
• Ram Size: 512 x 8
• Interface: I²C, SPI, UART
• Number Of I /o: 20
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Ic Function: Single Phase Energy Measurement IC
• Supply Voltage Range: 3.13V To 3.46V, 2.4V To 3.7V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

INTERRUPT FLAGS
The interrupt flags and status flags associated with the interrupt vectors are shown in Table 82 and Table 83. Most of the interrupts have
flags associated with them.
Table 82. Interrupt Flags
Interrupt Source
IE0
TF0
IE1
TF1
RI + TI
TF2 + EXF2
ITEMP (Temperature ADC)
IPSM (Power Supply)
IADE (Energy Measurement DSP)
1
Table 83. Status Flags
Interrupt Source
ITEMP (Temperature ADC)
ISPI/I2CI
IRTC (RTC Interval Timer)
WDT (Watchdog Timer)
1
A functional block diagram of the interrupt system is shown in
Figure 89. Note that the PSM interrupt is the only interrupt in
the highest priority level.
If an external wake-up event occurs to wake the ADE7116/
ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 from PSM2
mode, a pending external interrupt is generated. When the EX0
bit (Bit 0) or the EX1 bit (Bit 2) in the interrupt enable SFR (IE,
Address 0xA8) is set to enable external interrupts, the program
counter is loaded with the IE0 or IE1 interrupt vector. The IE0
and IE1 interrupt flags (Bit 1 and Bit 3, respectively) in the
Timer/Counter 0 and Timer/Counter 1 control SFR (TCON,
Address 0x88) are not affected by events that occur when the
8052 MCU core is shut down during PSM2. See the Power
Supply Management (PSM) Interrupt section.
The RTC, temperature ADC, and I
such that pending interrupts cannot be cleared without entering
their respective interrupt service routines. Clearing the RTC
midnight flags and alarm flags does not clear a pending RTC
This feature is not available in the ADE7116.
This feature is not available in the ADE7116.
1
1
N/A
SPI2CSTAT
SPI2CSTAT
TIMECON.7
TIMECON.2
WDCON.2
Flag
TCON.1
TCON.5
TCON.3
TCON.7
SCON.1
SCON.0
T2CON.7
T2CON.6
N/A
IPSMF.6
MIRQSTL.7
Flag
2
C/SPI interrupts are latched
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
IE0
TF0
IE1
TI
TF2
EXF2
FPSM
Bit Name
TF1
RI
N/A
ADEIRQFLAG
N/A
N/A
N/A
MIDNIGHT
ALARM
WDS
Bit Address
Rev. B | Page 95 of 152
Description
Temperature ADC interrupt. Does not have a status flag associated with it.
SPI interrupt status register.
I
RTC midnight flag.
RTC alarm flag.
Watchdog timeout flag.
Description
External interrupt 0.
Timer 0.
External interrupt 1.
Timer 1.
Transmit interrupt.
Receive interrupt.
Timer 2 overflow flag.
Timer 2 external flag.
Temperature ADC interrupt. Does not have an interrupt flag associated with it.
PSM interrupt flag.
Read MIRQSTH, MIRQSTM, MIRQSTL.
2
C interrupt status register.
interrupt. Similarly, clearing the I
Interrupt Status SFR (SPISTAT, Address 0xEA) does not cancel
a pending I
until the RTC or I
respective interrupt service routines are entered shortly
thereafter.
Figure 89 shows how the interrupts are cleared when the
interrupt service routines are entered. Some interrupts with
multiple interrupt sources are not automatically cleared;
specifically, the PSM, ADE, UART, and Timer 2 interrupt
vectors. Note that the INT0 and INT1 interrupts are only
cleared only if the external interrupt is configured to be
triggered by a falling edge by setting IT0 (Bit 0) in the
Timer/Counter 0 and Timer/Counter 1 control SFR (TCON,
Address 0x88). If INT0 or INT1 is configured to interrupt on a
low level, the interrupt service routine is reentered until the
respective pin goes high.
2
C/SPI interrupt. These interrupts remain pending
2
C/SPI interrupt vectors are enabled. Their
2
C/SPI status bits in the SPI