MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 78
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MPC8308VMAGD
Manufacturer Part Number
MPC8308VMAGD
Description
MPU POWERQUICC II PRO 473MAPBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8308VMAGD.pdf
(90 pages)
2.MPC8308VMAGD.pdf
(2 pages)
3.MPC8308VMAGD.pdf
(1170 pages)
4.MPC8308VMAGD.pdf
(14 pages)
Specifications of MPC8308VMAGD
Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
400MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
473-MAPBGA
Product
Network Processor
Data Rate
256 bps
Frequency
400 MHz
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Supply Current (max)
5 uA
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
0 C
Interface
I2C, JTAG, SPI
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8308VMAGD
Manufacturer:
FREESCAL
Quantity:
300
Company:
Part Number:
MPC8308VMAGD
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC8308VMAGD
Manufacturer:
FREESCALE
Quantity:
20 000
Company:
Part Number:
MPC8308VMAGD400/266
Manufacturer:
FREESCAL
Quantity:
300
Company:
Part Number:
MPC8308VMAGDA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Clocking
Table 55
(Table
21.2
The system PLL is controlled by the RCWL[SPMF] parameter.
encodings for the system PLL.
As described in
configuration word low select the ratio between the primary clock input (SYS_CLK_IN) and the internal
78
e300 core frequency ( core_clk )
Coherent system bus frequency ( csb_clk )
DDR2 memory bus frequency (MCK)
Local bus frequency (LCLK 0 )
Notes:
1. The SYS_CLK_IN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting csb_clk ,
2. The DDR data rate is 2x the DDR memory bus frequency.
3. The local bus frequency is 1/2, 1/4, or 1/8 of the lbc_clk frequency (depending on LCCR[CLKDIV]) which is in turn, 1x or 2x
MCK, LCLK0, and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies.
the csb_clk frequency (depending on RCWL[LBCM]).
2).
provides the operating frequencies for the device under recommended operating conditions
System PLL Configuration
Section 21, “Clocking,”
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2
Characteristic
3
RCWL[SPMF]
0110–1111
Table 55. Operating Frequencies for MPC8308
0000
0001
0010
0011
0100
0101
2
1
Table 56. System PLL Ratio
the LBCM, DDRCM, and SPMF parameters in the reset
csb_clk: SYS_CLK_IN
Reserved
Reserved
Reserved
Maximum Operating Frequency
2 : 1
3 : 1
4 : 1
5 : 1
Table 56
400
133
133
66
shows the multiplication factor
Freescale Semiconductor
MHz
MHz
MHz
MHz
Unit