MPC8313ECZQAFFB Freescale Semiconductor, MPC8313ECZQAFFB Datasheet - Page 39
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MPC8313ECZQAFFB
Manufacturer Part Number
MPC8313ECZQAFFB
Description
IC MPU POWERQUICC II PRO 516PBGA
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQAFFB.pdf
(100 pages)
Specifications of MPC8313ECZQAFFB
Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
333MHz
Voltage
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Package / Case
516-PBGA
Processor Series
MPC8xxx
Core
e300
Data Bus Width
32 bit
Development Tools By Supplier
MPC8313E-RDB
Maximum Clock Frequency
333 MHz
Operating Supply Voltage
1 V, 3.3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
I/o Voltage
1 V, 1.8 V, 2.5 V, 3.3 V
Minimum Operating Temperature
- 40 C
For Use With
MPC8313E-RDB - BOARD PROCESSOR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8313ECZQAFFB
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
9.2.2
The DC level requirement for the MPC8313E SerDes reference clock inputs is different depending on the
signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described
below.
Freescale Semiconductor
•
•
Differential mode
— The input amplitude of the differential clock must be between 400 and 1600 mV differential
— For external DC-coupled connection, as described in
— For external AC-coupled connection, there is no common mode voltage requirement for the
Single-ended mode
— The reference clock can also be single-ended. The SD_REF_CLK input amplitude
— The SD_REF_CLK input average voltage must be between 200 and 400 mV.
— To meet the input amplitude requirement, the reference clock inputs might need to be DC or
peak-to-peak (or between 200 and 800 mV differential peak). In other words, each signal wire
of the differential pair must have a single-ended swing less than 800 mV and greater than
200 mV. This requirement is the same for both external DC-coupled or AC-coupled
connection.
Receiver Characteristics,”
average voltage (common mode voltage) to be between 100 and 400 mV.
SerDes reference clock input requirement for the DC-coupled connection scheme.
clock driver. Since the external AC-coupling capacitor blocks the DC level, the clock driver
and the SerDes reference clock receiver operate in different command mode voltages. The
SerDes reference clock receiver in this connection scheme has its common mode voltage set to
XCOREV
the command mode voltage (XCOREV
requirement for AC-coupled connection scheme.
(single-ended swing) must be between 400 and 800 mV peak-to-peak (from V
SD_REF_CLK either left unconnected or tied to ground.
the SerDes reference clock input requirement for the single-ended signaling mode.
AC coupled externally. For the best noise performance, the reference of the clock could be DC
DC Level Requirement for SerDes Reference Clocks
MPC8313E PowerQUICC
SS
. Each signal wire of the differential inputs is allowed to swing below and above
Figure 23. Receiver of SerDes Reference Clocks
SD n _REF_CLK
SD n _REF_CLK
the maximum average current requirements sets the requirement for
™
II Pro Processor Hardware Specifications, Rev. 3
SS
50 Ω
50 Ω
).
Figure 25
Input
Amp
Section 9.2.1, “SerDes Reference Clock
shows the SerDes reference clock input
High-Speed Serial Interfaces (HSSI)
Figure 24
min
Figure 26
to V
shows the
max
shows
) with
39