MPC8313ECZQAFFB Freescale Semiconductor, MPC8313ECZQAFFB Datasheet - Page 79
![IC MPU POWERQUICC II PRO 516PBGA](/photos/6/77/67793/mpc8313eczqaffb_sml.jpg)
MPC8313ECZQAFFB
Manufacturer Part Number
MPC8313ECZQAFFB
Description
IC MPU POWERQUICC II PRO 516PBGA
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQAFFB.pdf
(100 pages)
Specifications of MPC8313ECZQAFFB
Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
333MHz
Voltage
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Package / Case
516-PBGA
Processor Series
MPC8xxx
Core
e300
Data Bus Width
32 bit
Development Tools By Supplier
MPC8313E-RDB
Maximum Clock Frequency
333 MHz
Operating Supply Voltage
1 V, 3.3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
I/o Voltage
1 V, 1.8 V, 2.5 V, 3.3 V
Minimum Operating Temperature
- 40 C
For Use With
MPC8313E-RDB - BOARD PROCESSOR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8313ECZQAFFB
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Table 65
conditions (see
20.1
The system PLL is controlled by the RCWL[SPMF] parameter.
encodings for the system PLL.
Freescale Semiconductor
provides the operating frequencies for the MPC8313E TEPBGAII under recommended operating
System PLL Configuration
TSEC1
TSEC2
Security Core, I
USB DR
PCI and DMA complex
e300 core frequency ( core_clk )
Coherent system bus frequency ( csb_clk )
DDR1/2 memory bus frequency (MCK)
Local bus frequency (LCLK n )
PCI input frequency (SYS_CLK_IN or PCI_CLK)
Notes:
1. The SYS_CLK_IN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be
2. The DDR data rate is 2x the DDR memory bus frequency.
3. The local bus frequency is 1/2, 1/4, or 1/8 of the lbc_clk frequency (depending on
Table
chosen such that the resulting csb_clk , MCK, LCLK[0:1], and core_clk frequencies do not
exceed their respective maximum or minimum operating frequencies. The value of
SCCR[ENCCM] and SCCR[USBDRCM] must be programmed such that the maximum
internal operating frequency of the security core and USB modules do not exceed their
respective value listed in this table.
LCCR[CLKDIV]), which is in turn, 1x or 2x the csb_clk frequency (depending on
RCWL[LBCM]).
MPC8313E PowerQUICC
2).
Unit
2
C, SAP, TPR
Characteristic
Table 65. Operating Frequencies for TEPBGAII
Table 66. System PLL Multiplication Factors
RCWL[SPMF]
Table 64. Configurable Clock Units
0000
0001
0010
3
™
1
II Pro Processor Hardware Specifications, Rev. 3
Frequency
Default
csb_clk
csb_clk
csb_clk
csb_clk
csb_clk
2
Multiplication Factor
Off, csb_clk, csb_clk /2, csb_clk /3
Off, csb_clk, csb_clk /2, csb_clk /3
Off, csb_clk, csb_clk /2, csb_clk /3
Off, csb_clk, csb_clk /2,
Off, csb_clk
System PLL
Operating Frequency
Reserved
Reserved
× 2
Maximum
Table 66
333
167
167
66
66
Options
shows the multiplication factor
csb_clk
Unit
MHz
MHz
MHz
MHz
MHz
/3
Clocking
79