MPC8315ECVRAGDA Freescale Semiconductor, MPC8315ECVRAGDA Datasheet - Page 60
![MPU POWERQUICC II PRO 620-PBGA](/photos/6/78/67837/mpc8315ecvragda_sml.jpg)
MPC8315ECVRAGDA
Manufacturer Part Number
MPC8315ECVRAGDA
Description
MPU POWERQUICC II PRO 620-PBGA
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8315VRADDA.pdf
(112 pages)
Specifications of MPC8315ECVRAGDA
Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
400MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
620-PBGA
Processor Series
MPC8xxx
Core
e300
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Leaded Process Compatible
Yes
Rohs Compliant
Yes
Peak Reflow Compatible (260 C)
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8315ECVRAGDA
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MPC8315ECVRAGDA
Manufacturer:
FREESCAL
Quantity:
36
Company:
Part Number:
MPC8315ECVRAGDA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC8315ECVRAGDA
Manufacturer:
FREESCALE
Quantity:
20 000
High-Speed Serial Interfaces (HSSI)
Figure 46
It assumes the DC levels of the clock driver are compatible with MPC8315E SerDes reference clock
input’s DC requirement.
15.2.4
The clock driver selected should provide a high quality reference clock with low phase noise and
cycle-to-cycle jitter. Phase noise less than 100KHz can be tracked by the PLL and data recovery loops and
is less of a problem. Phase noise above 15MHz is filtered by the PLL. The most problematic phase noise
occurs in the 1-15MHz range. The source impedance of the clock driver should be 50 Ω to match the
transmission line and reduce reflections which are a source of noise to the system.
60
Single-Ended
CLK Driver Chip
Clock Driver
LVPECL CLK
Driver Chip
Clock Driver
Clock Driver
Figure 45. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)
shows the SerDes reference clock connection reference circuits for a single-ended clock driver.
AC Requirements for SerDes Reference Clocks
CLK_Out
CLK_Out
CLK_Out
MPC8315E PowerQUICC
Figure 46. Single-Ended Connection (Reference Only)
33 Ω
R1
R1
100 Ω differential PWB trace
Total 50 Ω. Assume clock driver’s
output impedance is about 16 Ω.
R2
R2
50
100 Ω differential PWB trace
Ω
™
II Pro Processor Hardware Specifications, Rev. 0
10 nF
10 nF
SD_REF_CLK
SD_REF_CLK
SD_REF_CLK
SD_REF_CLK
50 Ω
50 Ω
50 Ω
50 Ω
MPC8315E
Freescale Semiconductor
MPC8315E
SerDes Refer.
CLK Receiver
SerDes Refer.
CLK Receiver