MPC8315ECVRAGDA Freescale Semiconductor, MPC8315ECVRAGDA Datasheet - Page 99
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MPC8315ECVRAGDA
Manufacturer Part Number
MPC8315ECVRAGDA
Description
MPU POWERQUICC II PRO 620-PBGA
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8315VRADDA.pdf
(112 pages)
Specifications of MPC8315ECVRAGDA
Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
400MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
620-PBGA
Processor Series
MPC8xxx
Core
e300
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Leaded Process Compatible
Yes
Rohs Compliant
Yes
Peak Reflow Compatible (260 C)
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8315ECVRAGDA
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MPC8315ECVRAGDA
Manufacturer:
FREESCAL
Quantity:
36
Company:
Part Number:
MPC8315ECVRAGDA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC8315ECVRAGDA
Manufacturer:
FREESCALE
Quantity:
20 000
As described in
configuration word low and the CFG_SYS_CLKIN_DIV configuration input signal select the ratio
between the primary clock input (SYS_CLKIN or PCI_CLK) and the internal coherent system bus clock
(csb_clk).
csb_clk to SYS_CLKIN/PCI_SYNC_IN ratios.
Freescale Semiconductor
Table 74
1
2
3
1
2
Section 24,
CFG_SYS_CLKIN_DIV
CFG_SYS_CLKIN_DIV
CFG_SYS_CLKIN_DIV select the ratio between SYS_CLKIN and PCI_SYNC_OUT.
SYS_CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
In the Host mode it does not matter if the value is High or Low.
CFG_SYS_CLKIN_DIV doubles csb_clk if set low.
SYS_CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
MPC8315E PowerQUICC
and
High/Low
at Reset
at Reset
High/Low
High/Low
High/Low
Table 75
High
High
High
High
Table 75. CSB Frequency Options for Agent Mode
“Clocking,” The LBIUCM, DDRCM, and SPMF parameters in the reset
Table 74. CSB Frequency Options for Host Mode
1
1
3
Table 73. System PLL Multiplication Factors
shows the expected frequency values for the CSB frequency for select
RCWL[SPMF]
0110–1111
0000
0001
0010
0011
0100
0101
™
SPMF
SPMF
0010
0011
0100
0101
0010
0011
0100
0101
II Pro Processor Hardware Specifications, Rev. 0
Input Clock
Input Clock
csb_clk :
csb_clk :
Multiplication Factor
Ratio
Ratio
2: 1
3: 1
4: 1
5: 1
2:1
3:1
4:1
5:1
System PLL
Reserved
Reserved
Reserved
2
2
× 2
× 3
× 4
× 5
120
120
24
96
25
Frequency (MHz)
frequency (MHz)
Input Clock
Input Clock
33.33
33.33
100
133
100
133
—
—
66.67
66.67
2
2
133
133
—
—
—
—
—
—
Clocking
99