XPC8240RZU250E Freescale Semiconductor, XPC8240RZU250E Datasheet - Page 7

• Manufacturer Part Number: XPC8240RZU250E
• Description: MCU HOST PROCESSOR 352-TBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC IIr

Specifications of XPC8240RZU250E

• Processor Type: MPC82xx PowerQUICC II 32-bit
• Speed: 200MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 352-TBGA
• Core Size: 32 Bit
• Program Memory Size: 32KB
• Cpu Speed: 250MHz
• Embedded Interface Type: I2C
• Digital Ic Case Style: TBGA
• No. Of Pins: 352
• Supply Voltage Range: 2.5V To 2.75V
• Rohs Compliant: No
• Family Name: MPC82XX
• Device Core Size: 32b
• Frequency (max): 250MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 2.625/2.6255V
• Operating Supply Voltage (max): 2.75625/2.756775V
• Operating Supply Voltage (min): 2.49375/2.494225V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 352
• Package Type: TBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

Figure 2 shows the supply voltage sequencing and separation cautions.
MPC8240 Integrated Processor Hardware Specifications
Notes:
1. Numbers associated with waveform separations correspond to caution numbers listed in Table 2.
2. Refer to Table 7 for additional information on PLL relock and reset signal assertion timing requirements.
3. Refer to Table 8 for additional information on reset configuration pin setup timing requirements.
4. For the device to be in the non-reset state, HRST_CPU/HRST_CTRL must transition from a logic 0 to a
3.3 V
2.5 V
5 V
0
Configuration Pins
HRST_CPU and
Figure 2. Supply Voltage Sequencing and Separation Cautions
HRST_CTRL
Power Supply Ramp Up
Voltage
Regulator
Delay
Freescale Semiconductor, Inc.
7
Reset
For More Information On This Product,
10
Go to: www.freescale.com
10
V
9
Maximum Rise Time Must be Less Than
DD
9
Stable
One External Memory Clock Cycle
6,8
See Note 1
Clock Cycles Setup Time
100 µs
Relock
Time
PLL
9 External Memory
2
Electrical and Thermal Characteristics
External Memory
HRST_CPU and
Clock Cycles
HRST_CTRL
Asserted 255
LV
OV
V
DD
DD
DD
/AV
@ 5 V
/GV
3
DD
4
DD
/AV
/(LV
2
DD
DD
2/LAV
@ 3.3 V - - - -)
VM = 1.4 V
DD
Time
7