MC68MH360AI33L Freescale Semiconductor, MC68MH360AI33L Datasheet - Page 108

• Manufacturer Part Number: MC68MH360AI33L
• Description: IC MPU QUICC 33MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360AI33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

6.6.2 State Registers
The QMC has two sets of state parameters—global and channel-specific. These registers
change if the QMC is running and the SCC is receiving clock.
Channel-specific
parameters—
HDLC and
transparent
Global state
parameter
Channel-specific
parameters—
HDLC
Channel-specific
parameters—
transparent
Notes:
1, 2
1
2
For more information on TSTATE and RSTATE, see Section 2.4.1, “Channel-Specific HDLC
Parameters.”
ZISTATE and ZDSTATE contain no meaningful parameters.
Offset
08
0E
28
2E
Offset
04
04
24
04
24
Freescale Semiconductor, Inc.
For More Information On This Product,
Tx internal data pointer
Tx internal byte count
Rx internal data pointer
Rx internal byte count
QMCSTATE
TSTATE
RSTATE
TSTATE
RSTATE
Table 6-7. Pointer Registers
Go to: www.freescale.com
Table 6-8. State Registers
Name
Name
QMC Supplement
Holds pointer to current data in buffer.
Holds down-counter of data left to transmit in this buffer
descriptor—loaded when the buffer descriptor is
opened with the BD length field.
Holds pointer to address inside the current buffer
where data will be received.
Holds down-counter of space left in this Rx buffer—
loaded when the BD is opened with the MRBLR field.
bit 0
• 1 if the QMC is stopped or has not started
• 0 if the QMC is running
bit 8— currently transmitting a frame
bit 9— buffer descriptor is currently open (data is being
transmitted from a BD)
bit 12— channel has been initialized and is running
bit 8—currently receiving a frame
bit 9— buffer descriptor is currently open (data is being
received into a BD)
bit 11— reception is halted
low word—current BD status word
bit 9— buffer descriptor is currently open (data is being
transmitted from a BD)
bit 12—channel has been initialized and is running.
bit 9— buffer descriptor is currently open (data is being
received into a BD)
bit 11— reception is halted
low word—current BD status word
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