MC68MH360AI33L Freescale Semiconductor, MC68MH360AI33L Datasheet - Page 20

• Manufacturer Part Number: MC68MH360AI33L
• Description: IC MPU QUICC 33MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360AI33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

1.4 The Time Slot Assigner and the QMC
The time slot assigner (TSA) in the MH devices is no different from the other versions. This
section discusses the new possibilities when using the TSA in combination with the QMC.
The QMC protocol can be executed in nonmultiplexed serial interface (NMSI) mode, but
the usual operating mode takes advantage of the programmable time slot assigner,.
A frame synchronization pulse alerts the time slot assigner to start counting clock pulses.
The user programs what bits are routed to the different internal serial channels. The TSA is
an intelligent multiplexer that restarts its sequence on every frame synchronization pulse.
External strobe signals allow other devices that do not have built-in time slot assigner
functions to participate in the TDM interface. This is very useful when interfacing to the
MC68302 or other telecommunication devices like codecs.
The time slot assigner is not limited to standard TDM lines. It is a flexible, programmable
device that allows the user to route any combination of bits and bytes to any channel. For
example, the user can transmit 3 bits from SCC2, skip 12 bytes, and then transmit another
17 bits from SCC1. This routing must be programmed into the TSA memory. The
complexity of the routing is limited only by the number of program entries in the TSA.
Ideal for TDM bridging applications, the MC68MH360 and MPC860MH have two
independent time slot assigners and physical interfaces. A complete set of independent
receive and transmit clock signals, as well as independent synchronization signals, are
available for each TDM.
1.5 The Serial Interface (SI)
Functions such as frame synchronization, loopback, echo, and inverted signals are
performed in the serial interface and cannot be achieved in NMSI mode. It is recommended
to use the serial interface even if only one SCC is used for the TDM bus.
• System interface
— On-chip bus arbitration for serial DMAs with no performance penalty
— Efficient bus usage (no bus usage for nonactive channels and active channels that
— Efficient control of the interrupts to the CPU
— Supports external buffer descriptors table
— Uses on-chip enlarged dual-ported RAM for parameter storage
have nothing to transmit)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
QMC Supplement