MC68MH360AI33L Freescale Semiconductor, MC68MH360AI33L Datasheet - Page 99

• Manufacturer Part Number: MC68MH360AI33L
• Description: IC MPU QUICC 33MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360AI33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Step 17. Initialize RxBDs. Prepare an adequate number of receive buffers at the location
addressed by RBASE. In the status word, set the E bit, set the I bit if interrupts are required
and set the W bit for the last buffer descriptor. The data length is normally cleared, and the
buffer pointer is set to a location in external memory. See Section 5.1, “Receive Buffer
Descriptor,” for more information. Repeat for each enabled channel.
Step 18. Initialize TxBDs. Prepare an adequate number of transmit buffers at the location
addressed by TBASE. In the status word, set the R bit, set the I bit if interrupts are required,
and set the W bit for the last buffer descriptor. Other options are available and may be set
or cleared depending on the application. The data length is written with the number of bytes
to transmit, and the buffer pointer is set to a location in external memory. See Section 5.2,
“Transmit Buffer Descriptor,” for more information. Repeat for each enabled channel.
Step 19. Initialize the circular interrupt table. If interrupts are required, initialize the
interrupt table as explained in Chapter 4, “QMC Exceptions.” Clear the V and W bits, but
make sure to set the last entry’s W bit.
Step 20. Initialize the channel mode register CHAMR (see Table 6-6). For more
information see Section 2.4.1.1, “CHAMR—Channel Mode Register (HDLC),” for HDLC
mode and Section 2.4.2.1, “CHAMR—Channel Mode Register (Transparent Mode),” for
transparent mode.
MODE
RD/0
1/IDLM
ENT
SYNC
POL
CRC
NOF
• MFLR/MRBLR: MFLR (HDLC mode)—application-dependent.
• TRNSYNC: transparent synchronization, system-specific.
Name
MRBLR (transparent mode)—must be divisible by 4 and large (>30) for better
performance.
ch[x].MFLR = 60;
Freescale Semiconductor, Inc.
Number of Bits
For More Information On This Product,
1
1
1
1
1
1
1
4
Table 6-6. CHAMR Bit Settings
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Chapter 6. QMC Initialization
0—transparent; 1—HDLC
Transparent only: reverse data
HDLC only: idle mode
Enable transmit
Transparent only: synchronization
Enable polling
HDLC only: CRC
Minimum number of flags
Description
Setting
X
X
X
X
X
X
0
0