MC68360EM25VL Freescale Semiconductor, MC68360EM25VL Datasheet - Page 129
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
MC68360EM25VL
Manufacturer Part Number
MC68360EM25VL
Description
IC MPU QUICC 25MHZ 240-FQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360EM25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
240-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68360EM25VL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68360EM25VL
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
- Current page: 129 of 962
- Download datasheet (4Mb)
4.6.2 Bus Grant
The QUICC supports operand coherency; thus, if an operand transfer requires multiple bus
cycles, the QUICC does not release the bus until the entire transfer is complete. The asser-
tion of BG is therefore subject to the following constraints:
Externally, the BG signal can be routed through a daisy-chained network or a priority-
encoded network. The QUICC is not affected by the method of arbitration as long as the pro-
tocol is obeyed.
4.6.3 Bus Grant Acknowledge
An external device cannot request and be granted the external bus while another device is
the active bus master. A device that asserts BGACK remains the bus master until it negates
BGACK. BGACK should not be negated until all required bus cycles are completed. Bus
mastership is terminated at the negation of BGACK. When no other device requests the bus
after BGACK is negated, the QUICC will regain bus mastership.
The minimum time for the first bus cycle after BGACK negation depends on internal syn-
chronization and internal bus arbitration. This timing is therefore subject to the following con-
straints:
• The minimum time for BG assertion after BR is asserted depends on internal synchro-
• When working in synchronous mode (ASTM bit in the MCR is set), the minimum time
• During an external operand transfer, the QUICC does not assert BG until after the last
• During an external operand transfer, the QUICC does not assert BG as long as RMC is
• If the show cycle bits SHEN1–SHEN0 = 1x and if one of the QUICC internal masters is
• If SHEN1–SHEN0 = 00 and if one of the QUICC internal masters is making internal ac-
• If SHEN1–SHEN0 = 01, the QUICC does not assert BG to an external master.
• When working in synchronous mode (ASTM bit in the MCR is set) and SHEN0–SHEN1
• When working in asynchronous mode (ASTM bit in the MCR is cleared) and SHEN0–1
• If SHEN1–SHEN0 = 1 , another clock is added for internal bus arbitration.
nization.
can be one clock.
cycle of the transfer (determined by SIZx and DSACKx).
asserted.
making internal accesses, the QUICC does not assert BG until the transfer is terminat-
ed.
cesses, the external bus is granted away, and the QUICC continues to execute internal
bus cycles. In this case, the arbitration overhead (external bus idle time) is minimal.
= 00 and one of the QUICC internal masters requests an external accesses, the mini-
mum time can be one clock.
= 00 and one of the QUICC internal masters requests an external accesses, the mini-
mum time depends on internal synchronization plus one clock.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
Bus Operation
Related parts for MC68360EM25VL
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![MC68360](/images/manufacturer_photos/0/2/263/freescale_semiconductor__inc_tmb.jpg)
Part Number:
Description:
Manufacturer:
Freescale Semiconductor, Inc
Datasheet:
![AN2036](/images/no-image3.png)
Part Number:
Description:
MC68360 MC68360 Multiple Ethernet Channels on the QUICC
Manufacturer:
Motorola / Freescale Semiconductor
![AN2035](/images/no-image3.png)
Part Number:
Description:
MC68360 Implementing an 8 bit Eprom for an MC68EC040-MC68360 System
Manufacturer:
Motorola / Freescale Semiconductor
![AN2038](/images/no-image3.png)
Part Number:
Description:
MC68360 Interfacing the MC68060 to the MC68360
Manufacturer:
Motorola / Freescale Semiconductor
![AN2040](/images/no-image3.png)
Part Number:
Description:
MC68360 MC68360 RAM Microcode Package Option Overview
Manufacturer:
Motorola / Freescale Semiconductor
![AN2045](/images/no-image3.png)
Part Number:
Description:
MC68360 MC68360 CPM-CPU Interaction
Manufacturer:
Motorola / Freescale Semiconductor
![AN2046](/images/no-image3.png)
Part Number:
Description:
MC68360 Interfacing SDRAM to the MC68360 QUICC Device
Manufacturer:
Motorola / Freescale Semiconductor
![AN2030](/images/no-image3.png)
Part Number:
Description:
MC68360 Interfacing the QUICC to a MCM516400 (4Mx4 10-12 column-row) DRAM
Manufacturer:
Motorola / Freescale Semiconductor
![AN2031](/images/no-image3.png)
Part Number:
Description:
MC68360 Interfacing the 68360 (QUICC) to T1-E1 Systems
Manufacturer:
Motorola / Freescale Semiconductor
![AN2032](/images/no-image3.png)
Part Number:
Description:
MC68360 Multiple QUICC Design Concept
Manufacturer:
Motorola / Freescale Semiconductor
![MC14560BCP](/images/manufacturer_photos/0/2/263/freescale_semiconductor__inc_tmb.jpg)
Part Number:
Description:
Manufacturer:
Freescale Semiconductor, Inc
Datasheet:
![MC12034AP](/images/manufacturer_photos/0/2/263/freescale_semiconductor__inc_tmb.jpg)
Part Number:
Description:
Manufacturer:
Freescale Semiconductor, Inc
Datasheet:
![MPIC2112P](/images/manufacturer_photos/0/2/263/freescale_semiconductor__inc_tmb.jpg)
Part Number:
Description:
Manufacturer:
Freescale Semiconductor, Inc
Datasheet:
![MC14520BCP](/images/manufacturer_photos/0/2/263/freescale_semiconductor__inc_tmb.jpg)
Part Number:
Description:
Manufacturer:
Freescale Semiconductor, Inc
Datasheet:
![MC12026AP](/images/manufacturer_photos/0/2/263/freescale_semiconductor__inc_tmb.jpg)
Part Number:
Description:
Manufacturer:
Freescale Semiconductor, Inc
Datasheet: