MC68360EM25VL Freescale Semiconductor, MC68360EM25VL Datasheet - Page 625
MC68360EM25VL
Manufacturer Part Number
MC68360EM25VL
Description
IC MPU QUICC 25MHZ 240-FQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360EM25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
240-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68360EM25VL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68360EM25VL
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
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R—Ready
Bits 14, 10, 8–2, 0—Reserved
W—Wrap (Final BD in Table)
I—Interrupt
L— Last in Message
CM—Continuous Mode
OFFSET + 0
OFFSET + 2
OFFSET + 4
OFFSET + 6
NOTE : Entries in boldface must be initialized by the user
0 = The data buffer associated with this BD is not ready for transmission. The user is
1 = The data buffer, which has been prepared for transmission by the user, has not
0 = This is not the last BD in the Tx BD table.
1 = This is the last BD in the Tx BD table. After this buffer has been used, the CP will
0 = No interrupt is generated after this buffer has been serviced.
1 = The TX or TXE bit in the event register will be set when this buffer has been ser-
0 = The last byte in the buffer is not the last byte in the transmitted transparent frame.
1 = The last byte in this buffer is the last byte in the transmitted transparent frame. After
0 = Normal operation.
1 = The R-bit is not cleared by the CP after this BD is closed, allowing the associated
free to manipulate this BD or its associated data buffer. The CP clears this bit after
the buffer has been transmitted or after an error condition is encountered.
been transmitted or is currently being transmitted. No fields of this BD may be writ-
ten by the user once this bit is set.
receive incoming data into the first BD in the table (the BD pointed to by TBASE).
The number of Tx BDs in this table is programmable and is determined by the
W-bit and the overall space constraints of the dual-port RAM.
viced. TX and TXE can cause interrupts if they are enabled.
Data from the next transmit buffer (if ready) will be transmitted immediately follow-
ing the last byte of this buffer.
this buffer is transmitted, the transmitter will require synchronization before the
next buffer will be transmitted.
data buffer to be retransmitted automatically when the CP next accesses this BD.
However, the R-bit will be cleared if an error occurs during transmission, regard-
less of the CM bit.
15
R
14
—
13
W
Freescale Semiconductor, Inc.
For More Information On This Product,
12
I
11
L
MC68360 USER’S MANUAL
Go to: www.freescale.com
10
—
CM
TX DATA BUFFER POINTER
9
DATA LENGTH
—
8
—
7
Serial Management Controllers (SMCs)
—
6
—
5
—
4
—
3
—
2
UN
1
—
0
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