MC68360EM25VL Freescale Semiconductor, MC68360EM25VL Datasheet - Page 288
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MC68360EM25VL
Manufacturer Part Number
MC68360EM25VL
Description
IC MPU QUICC 25MHZ 240-FQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360EM25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
240-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68360EM25VL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68360EM25VL
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
- Current page: 288 of 962
- Download datasheet (4Mb)
System Integration Module (SIM60)
6.9.3.12 BREAKPOINT ADDRESS REGISTER (BKAR). This register contains the 32-bit
breakpoint address used in the breakpoint address match function. Its contents are only
valid if the valid bit is set in the BKCR. BKAR is undefined at reset.
6.9.3.13 BREAKPOINT CONTROL REGISTER (BKCR). This register contains miscella-
neous bits required for the breakpoint address match function. BKCR is cleared at reset.
Bits 31–20—Reserved
BAS—Breakpoint Acknowledge Support
BUSS—Bus Select
6-44
BA31
BA15
SIZM
31
15
31
15
for entering into low-power mode). Clearing this bit switches the general system clock to
the DFNH value. CSRC is cleared at hardware reset.
—
This bit determines whether to support the CPU32+ breakpoint acknowledge cycle by as-
serting BERR or ignore the breakpoint acknowledge cycle by allowing it to be handled by
the external bus.
This bit determines whether the breakpoint logic will use the IMB value or the external bus
value to detect breakpoint match.
U
U
0
0 = General system clock is determined by the DFNH value.
1 = General system clock is determined by the DFNL value.
0 = No action taken during CPU32+ breakpoint acknowledge cycles.
1 = Assert BERR during CPU32+ breakpoint acknowledge cycles.
0 = Use the IMB.
1 = Use the external bus. A0 and A1 are masked from the comparison.
BA30
BA14
SIZ1
30
—
14
30
14
U
U
0
BA29
BA13
SIZ0
29
13
—
Do not assert this bit if the QUICC is in slave mode.
29
13
0
U
U
BA28
BA12
NEG
28
—
12
28
12
0
U
U
BA27
BA11
MA1
27
11
—
Freescale Semiconductor, Inc.
27
11
0
U
U
For More Information On This Product,
BA26
BA10
MA0
26
10
—
26
10
0
U
U
MC68360 USER’S MANUAL
Go to: www.freescale.com
BA25
AS8
BA9
25
—
25
0
U
U
9
9
BA24
AS7
BA8
24
—
24
NOTE
8
0
U
U
8
BA23
AS6
BA7
23
—
23
U
U
7
0
7
BA22
AS5
BA6
22
—
22
6
0
U
U
6
BA21
AS4
BA5
21
—
21
U
U
5
0
5
BA20
AS3
BA4
20
—
20
4
0
U
U
4
BA19
BAS
AS2
BA3
19
19
U
U
0
3
0
3
BUSS
BA18
AS1
BA2
18
18
0
2
0
U
U
2
RW1
BA17
AS0
BA1
17
17
0
1
0
U
1
U
BA16
RW0
BA0
16
16
0
0
V
0
U
U
0
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