MC68360EM25VL Freescale Semiconductor, MC68360EM25VL Datasheet - Page 266
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MC68360EM25VL
Manufacturer Part Number
MC68360EM25VL
Description
IC MPU QUICC 25MHZ 240-FQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360EM25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
240-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68360EM25VL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68360EM25VL
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
- Current page: 266 of 962
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System Integration Module (SIM60)
6.7.1 Initial Configuration
The QUICC has three configuration (CONFIG) pins that are sampled during system (or
power-up) reset to select the initial size of the global chip select and whether the QUICC is
in the normal (CPU32+ enabled) mode or the slave (CPU32+ disabled) mode (see Table 6-
2).
See 6.10 Memory Controller for a description of the global chip select and 6.8 Slave (Disable
CPU32+) Mode for a description of slave mode. In normal mode, the global chip select can
initially assume the boot ROM port size to be either 8, 16, or 32 bits. In the slave mode, the
global chip select can be enabled with 8, 16, or 32 bits, or the global chip select can be dis-
abled. The global chip select would normally be disabled if another QUICC or processor was
providing the boot ROM chip select function.
6.7.2 Port D
If the user configures a 16-bit data bus by driving a zero voltage on the PRTY3 pin during
system reset, then the D0–D15 pins are not used as a data bus, but are referred to as port
D. At this time, port D is not available for general-purpose I/O or any other alternate function
on the QUICC. In the future, these pins may be defined to have an additional function in 16-
bit data bus mode.
6-22
CONFIG2
/FREEZE
0
0
0
0
1
1
1
1
Configuration Pins
All accesses to the QUICC internal RAM and registers (including
MBAR) by an external master are asynchronous to the QUICC
clock. Read and write accesses are with three wait states, and
DSACK is asserted by the QUICC assuming three-wait-state ac-
cesses.
CONFIG1
/BCLRO
0
0
1
1
0
0
1
1
Freescale Semiconductor, Inc.
Table 6-2. QUICC Initial Configuration
CONFIG0
/RMC
For More Information On This Product,
0
1
0
1
0
1
0
1
MC68360 USER’S MANUAL
Slave mode; global chip select 8-bit size; MBAR at $003FF00.
Slave mode; global chip select 32-bit size; MBAR at $003FF00; not
MC68040 companion mode; BR output, BG input.
Slave mode; global chip select 16-bit size; MBAR at $003FF00.
MC68040 companion mode; global chip select 32-bit size; MBAR at
$003FF00; BR input, BG output.
CPU32+ enabled; global chip select 32-bit size; MBAR at $003FF00.
CPU32+ enabled; global chip select 16-bit size; MBAR at $003FF00.
Slave mode; global chip select disabled; MBAR at $003FF04.
CPU32+ enabled; global chip select 8-bit size; MBAR at $003FF00.
Go to: www.freescale.com
NOTE
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