MC68360ZP25L Freescale Semiconductor, MC68360ZP25L Datasheet - Page 10
MC68360ZP25L
Manufacturer Part Number
MC68360ZP25L
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360ZP25L
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
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Quantity:
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MC68360ZP25LR2
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Table of Contents
Paragraph
Number
5.5.4.1
5.5.4.2
5.5.4.3
5.6
5.6.1
5.6.1.1
5.6.1.2
5.6.1.3
5.6.2
5.6.2.1
5.6.2.2
5.6.2.2.1
5.6.2.2.2
5.6.2.2.3
5.6.2.3
5.6.2.4
5.6.2.5
5.6.2.5.1
5.6.2.5.2
5.6.2.5.3
5.6.2.6
5.6.2.7
5.6.2.7.1
5.6.2.7.2
5.6.2.8
5.6.2.8.1
5.6.2.8.2
5.6.2.8.3
5.6.2.8.4
5.6.2.8.5
5.6.2.8.6
5.6.2.8.7
5.6.2.8.8
5.6.2.8.9
5.6.2.8.10
5.6.2.8.11
5.6.2.8.12
5.6.2.8.13
5.6.2.8.14
5.6.2.8.15
5.6.2.8.16
5.6.3
5.6.3.1
5.6.3.2
5.6.3.3
vi
Four-Word Stack Frame ........................................................................5-56
Six-Word Stack Frame...........................................................................5-56
Bus Error Stack Frame ..........................................................................5-56
Development Support ............................................................................5-59
CPU32+ Integrated Development Support ............................................5-59
Background Debug Mode (BDM) Overview...........................................5-59
Deterministic Opcode Tracking Overview..............................................5-60
On-Chip Hardware Breakpoint Overview...............................................5-60
Background Debug Mode ......................................................................5-60
Enabling BDM ........................................................................................5-60
BDM Sources.........................................................................................5-61
External BKPT Signal ............................................................................5-62
BGND Instruction ...................................................................................5-62
Double Bus Fault ...................................................................................5-62
Entering BDM.........................................................................................5-62
Command Execution..............................................................................5-62
BDM Registers.......................................................................................5-63
Fault Address Register (FAR)................................................................5-63
Return Program Counter (RPC).............................................................5-63
Current Instruction Program Counter (PCC)..........................................5-63
Returning from BDM ..............................................................................5-63
Serial Interface.......................................................................................5-63
CPU Serial Logic....................................................................................5-65
Development System Serial Logic .........................................................5-66
Command Set ........................................................................................5-68
Command Format ..................................................................................5-68
Command Sequence Diagram...............................................................5-69
Command Set Summary........................................................................5-69
Read A/D Register (RAREG/RDREG)...................................................5-71
Write A/D Register (WAREG/WDREG) .................................................5-71
Read System Register (RSREG)...........................................................5-71
Write System Register (WSREG) ..........................................................5-72
Read Memory Location (READ) ............................................................5-73
Write Memory Location (WRITE) ...........................................................5-74
Dump Memory Block (DUMP)................................................................5-75
Fill Memory Block (FILL) ........................................................................5-76
Resume Execution (GO)........................................................................5-77
Call User Code (CALL) ..........................................................................5-77
Reset Peripherals (RST)........................................................................5-79
No Operation (NOP) ..............................................................................5-79
Future Commands .................................................................................5-80
Deterministic Opcode Tracking..............................................................5-80
Instruction Fetch (IFETCH) ....................................................................5-80
Instruction Pipe (IPIPE1–IPIPE0) ..........................................................5-80
Opcode Tracking during Loop Mode......................................................5-82
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
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