MC68360ZP25L Freescale Semiconductor, MC68360ZP25L Datasheet - Page 113
MC68360ZP25L
Manufacturer Part Number
MC68360ZP25L
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360ZP25L
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
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The interrupt acknowledge cycle is a read cycle. It differs from the read cycle described in
4.3.1 Read Cycle in that it accesses the CPU address space. Specifically, the differences
are as follows:
The responding device places the vector number on the data bus during the interrupt
acknowledge cycle. Beyond this, the cycle is terminated normally with DSACKx.
Figure 4-26 is a flowchart of the interrupt acknowledge cycle; Figure 4-27 shows the timing
for an interrupt acknowledge cycle terminated with DSACKx.
1. FC3–FC0 are set to $7 (FC3/FC2/FC1/FC0 = 0111) for CPU address space.
2. A3, A2, and A1 are set to the interrupt request level, and the IACKx strobe correspond-
3. The CPU32+ space type field (A19–A16) is set to $F (interrupt acknowledge).
4. Other address signals (A31–A20, A15–A4, and A0) are set to one.
ing to the current interrupt level is asserted. (Either the function codes and address sig-
nals or the IACKx strobes can be monitored to determine that an interrupt
acknowledge cycle is in progress and the current interrupt level.)
1) PLACE VECTOR NUMBER ON LEAST SIGNIFICANT
2) ASSERT DSACKx (OR AVEC IF NO VECTOR
1) NEGATE DSACKx
BYTE OF DATA PORT (DEPENDS ON
PORT SIZE)
NUMBER)
PROVIDE VECTOR NUMBER
INTERRUPTING DEVICE
REQUEST INTERRUPT
Figure 4-26. Interrupt Acknowledge Cycle Flowchart
RELEASE
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
1) SYNCHRONIZE IRQ7–IRQ1
2) COMPARE IRQ7–IRQ1 TO MASK LEVEL AND
3) ASSERT BCLRO
4) PLACE INTERRUPT LEVEL ON A1–A3;
5) SET R/W TO READ
6) SET FC3–FC0 TO 0111
7) DRIVE SIZx PINS TO INDICATE A ONE-BYTE
8) NEGATE BCLRO.
9) ASSERT AS, DS, AND OE
1) LATCH VECTOR NUMBER
2) NEGATE AS, DS, AND OE
WAIT FOR INSTRUCTION TO COMPLETE
TYPE FIELD (A19–A16) = $F
TRANSFER
ACQUIRE VECTOR NUMBER
START NEXT CYCLE
GRANT INTERRUPT
QUICC
Bus Operation
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