MPC7410RX500LE Freescale Semiconductor, MPC7410RX500LE Datasheet - Page 14

• Manufacturer Part Number: MPC7410RX500LE
• Description: IC MPU 32BIT 500MHZ PPC 360-CBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC7410RX500LE

• Processor Type: MPC74xx PowerPC 32-Bit
• Speed: 500MHz
• Voltage: 1.8V
• Mounting Type: Surface Mount
• Package / Case: 360-FCCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Electrical and Thermal Characteristics
4.2.1
Table 7
Figure 3
14
At recommended operating conditions (see
Processor frequency
VCO frequency
SYSCLK frequency
SYSCLK cycle time
SYSCLK rise and fall time
SYSCLK duty cycle
measured at OV
SYSCLK jitter
Internal PLL-relock time
Notes:
1. Caution: The SYSCLK frequency and PLL_CFG[0:3] settings must be chosen such that the resulting SYSCLK (bus)
2. Rise and fall times measurement are determined by the slew rates of the bus interface, rather than by time. As a result, the
3. Timing is guaranteed by design and characterization.
4. This represents total input jitter—short- and long-term combined—and is guaranteed by design.
5. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for PLL
frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to the PLL_CFG[0:3] signal description in
settings.
0.5 ns rise/fall time spec of the 1.8- and 2.5-V bus interfaces is equivalent to the 1 ns rise/fall time of the 3.3-V bus interface.
Both interfaces required a 2 V/ns slew rate. The slew rate is measured as a 1-V change (from 0.2 to 1.2 V) in 0.5 ns for the
1.8- and 2.5-V bus interfaces, whereas the 3.3-V bus interface required a 2-V change (from 0.4 to 2.4 V) in 1 ns.
lock after a stable V
the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted
for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.
Characteristic
provides the clock AC timing specifications as defined in
provides the SYSCLK input timing diagram.
Clock AC Specifications
SYSCLK
DD
/2
DD
and SYSCLK are reached during the power-on reset sequence. This specification also applies when
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
t
KHKL
t
KR
Symbol
f
t
SYSCLK
SYSCLK
VM
f
f
and t
VCO
core
/t
—
—
Table
t
Figure 3. SYSCLK Input Timing Diagram
Table 7. Clock AC Timing Specifications
SYSCLK
KHKL
KF
t
3)
SYSCLK
VM
Min
350
700
7.5
33
40
VM = Midpoint Voltage (OV DD /2)
—
—
—
400 MHz
Maximum Processor Core Frequency
±150
Max
400
800
133
100
0.5
30
60
VM
Section 8.1, “PLL Configuration,”
CV IL
Min
350
700
7.5
33
40
—
—
—
Figure
450 MHz
CV IH
±150
Max
3.
450
900
133
100
0.5
30
60
t
KR
Min
350
700
7.5
33
40
—
—
—
500 MHz
for valid PLL_CFG[0:3]
1000
±150
Max
500
133
100
0.5
30
60
Freescale Semiconductor
t
KF
Unit
MHz
MHz
MHz
ns/V
ns
ps
μs
%
Notes
—
1
1
1
2
3
4
5