MPC7410RX500LE Freescale Semiconductor, MPC7410RX500LE Datasheet - Page 4

• Manufacturer Part Number: MPC7410RX500LE
• Description: IC MPU 32BIT 500MHZ PPC 360-CBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC7410RX500LE

• Processor Type: MPC74xx PowerPC 32-Bit
• Speed: 500MHz
• Voltage: 1.8V
• Mounting Type: Surface Mount
• Package / Case: 360-FCCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Features
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Decode
— Register file access
— Forwarding control
— Partial instruction decode
Completion
— Eight-entry completion buffer
— Instruction tracking and peak completion of two instructions per cycle
— Completion of instructions in program order while supporting out-of-order instruction execution,
Fixed point units (FXUs) that share 32 GPRs for integer operands
— Fixed point unit 1 (FXU1)—multiply, divide, shift, rotate, arithmetic, logical
— Fixed point unit 2 (FXU2)—shift, rotate, arithmetic, logical
— Single-cycle arithmetic, shifts, rotates, logical
— Multiply and divide support (multi-cycle)
— Early out multiply
Three-stage floating-point unit and a 32-entry FPR file
— Support for IEEE Std 754™ single- and double-precision floating-point arithmetic
— Three-cycle latency, one-cycle throughput (single- or double-precision)
— Hardware support for divide
— Hardware support for denormalized numbers
— Time deterministic non-IEEE mode
System unit
— Executes CR logical instructions and miscellaneous system instructions
— Special register transfer instructions
AltiVec unit
— Full 128-bit data paths
— Two dispatchable units: vector permute unit and vector ALU unit.
— Contains its own 32-entry, 128-bit vector register file (VRF) with 6 renames
— The vector ALU unit is further subdivided into the vector simple integer unit (VSIU), the vector
— Fully pipelined
Load/store unit
— One-cycle load or store cache access (byte, half word, word, double word)
— Two-cycle load latency with 1-cycle throughput
— Effective address generation
— Hits under misses (multiple outstanding misses)
— Single-cycle unaligned access within double-word boundary
— Alignment, zero padding, sign extend for integer register file
— Floating-point internal format conversion (alignment, normalization)
— Sequencing for load/store multiples and string operations
completion serialization, and all instruction flow changes
complex integer unit (VCIU), and the vector floating-point unit (VFPU).
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor