CS4245-CQZ Cirrus Logic Inc, CS4245-CQZ Datasheet - Page 31

• Manufacturer Part Number: CS4245-CQZ
• Description: IC CODEC AUD STER 104DB 48LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS4245-CQZ

• Package / Case: 48-LQFP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 104 / 104
• Voltage - Supply, Analog: 3.13 V ~ 5.25 V
• Voltage - Supply, Digital: 3.13 V ~ 5.25 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 12
• Number Of Dac Outputs: 4
• Conversion Rate: 192 KSPS
• Interface Type: Serial (I2C, SPI)
• Resolution: 24 bit
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 2 ADC/2 DAC
• Thd Plus Noise: - 95 dB ADC / - 90 dB DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1501 - BOARD EVAL FOR CS4245 CODEC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1034

DS656F2
4.2.3
4.2.4
LRCK
Mode
(kHz)
176.4
44.1
88.2
128
192
32
48
64
96
in Master Mode and receive the proper clocks in Slave Mode.
sample rates and the required MCLK and LRCK frequencies.
Master Mode
As a clock master, LRCK and SCLK will operate as outputs. The two serial ports may be independently
placed into Master or Slave mode. Each LRCK and SCLK is internally derived from its respective MCLK
with LRCK equal to Fs and SCLK equal to 64 x Fs as shown in
Slave Mode
In Slave Mode, SCLK and LRCK operate as inputs. Each serial port may be independently placed into
Slave Mode. The Left/Right clock signal must be equal to the sample rate, Fs. If operating in Asynchro-
nous Mode, LRCK1 must be synchronously derived from MCLK1 and LRCK2 must be synchronously de-
rived from MCLK2. If operating in Synchronous Mode, LRCK1, and LRCK2 must be synchronously
11.2896
12.2880
8.1920
64x
-
-
-
-
-
-
12.2880
16.9344
18.4320
96x
-
-
-
-
-
-
MCLK1
MCLK2
MCLK1 Freq Bits
MCLK2 Freq Bits
11.2896
12.2880
16.3840
22.5792
24.5760
8.1920
128x
QSM
-
-
-
Table 2. Common Clock Frequencies
÷1.5
÷1.5
Figure 13. Master Mode Clocking
÷1
÷2
÷3
÷4
÷1
÷2
÷3
÷4
12.2880
16.9344
18.4320
24.5760
33.8680
36.8640
192x
000
001
010
011
100
000
001
010
011
100
-
-
-
ASynch Bit
MCLK (MHz)
0
1
12.2880
16.3840
22.5792
24.5760
32.7680
45.1584
49.1520
11.2896
8.1920
256x
ADC_FM Bits
DAC_FM Bits
÷256
÷128
÷256
÷128
÷64
÷64
÷4
÷2
÷1
÷4
÷2
÷1
12.2880
16.9344
18.4320
24.5760
33.8680
36.8640
384x
00
01
10
00
01
10
00
01
10
00
01
10
Table 2
-
-
-
Figure
DSM
LRCK1
SCLK1
LRCK2
SCLK2
illustrates several standard audio
13.
16.3840
22.5792
24.5760
32.7680
45.1584
49.1520
512x
-
-
-
24.5760
33.8680
36.8640
768x
-
-
-
-
-
-
SSM
CS4245
32.7680
45.1584
49.1520
1024x
-
-
-
-
-
-
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