CS4245-CQZ Cirrus Logic Inc, CS4245-CQZ Datasheet - Page 44

• Manufacturer Part Number: CS4245-CQZ
• Description: IC CODEC AUD STER 104DB 48LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS4245-CQZ

• Package / Case: 48-LQFP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 104 / 104
• Voltage - Supply, Analog: 3.13 V ~ 5.25 V
• Voltage - Supply, Digital: 3.13 V ~ 5.25 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 12
• Number Of Dac Outputs: 4
• Conversion Rate: 192 KSPS
• Interface Type: Serial (I2C, SPI)
• Resolution: 24 bit
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 2 ADC/2 DAC
• Thd Plus Noise: - 95 dB ADC / - 90 dB DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1501 - BOARD EVAL FOR CS4245 CODEC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1034

44
6.4.2
6.4.3
6.4.4
6.4.5
6.5
6.5.1
Reserved
7
MCLK Frequency - Address 05h
ADC Digital Interface Format (Bit 4)
Function:
The required relationship between LRCK1, SCLK1 and SDOUT is defined by the ADC Digital Interface
Format bit. The options are detailed in
Mute ADC (Bit 2)
Function:
When this bit is set, the serial audio output of the both ADC channels is muted.
ADC High-Pass Filter Freeze (Bit 1)
Function:
When this bit is set, the internal high-pass filter is disabled.The current DC offset value will be frozen and
continue to be subtracted from the conversion result. See
page 32.
ADC Master / Slave Mode (Bit 0)
Function:
This bit selects either master or slave operation for serial audio port 1. Setting this bit selects Master
Mode, while clearing this bit selects Slave Mode.
Master Clock 1 Frequency (Bits 6:4)
Function:
Sets the frequency of the supplied MCLK1 signal. See
ADC_DIF
0
1
MCLK1
Freq2
6
MCLK1 Divider
Reserved
Reserved
Left-Justified, up to 24-bit data (default)
÷ 1.5
÷ 1
÷ 2
÷ 3
÷ 4
MCLK1
Freq1
5
I²S, up to 24-bit data
Table 10. ADC Digital Interface Formats
Description
Table 11. MCLK 1 Frequency
MCLK1 Freq2 MCLK1 Freq1 MCLK1 Freq0
MCLK1
Freq0
Table 10
4
0
0
0
0
1
1
1
and may be seen in
Reserved
3
Table 11
“High-Pass Filter and DC Offset Calibration” on
0
0
1
1
0
0
1
for the appropriate settings.
Format
MCLK2
Freq2
0
1
2
Figure 7
0
1
0
1
0
1
x
and
MCLK2
Freq1
Figure
Figure
1
7
8
8.
CS4245
MCLK2
Freq0
DS656F2
0