CS4245-CQZ Cirrus Logic Inc, CS4245-CQZ Datasheet - Page 32

• Manufacturer Part Number: CS4245-CQZ
• Description: IC CODEC AUD STER 104DB 48LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS4245-CQZ

• Package / Case: 48-LQFP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 104 / 104
• Voltage - Supply, Analog: 3.13 V ~ 5.25 V
• Voltage - Supply, Digital: 3.13 V ~ 5.25 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 12
• Number Of Dac Outputs: 4
• Conversion Rate: 192 KSPS
• Interface Type: Serial (I2C, SPI)
• Resolution: 24 bit
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 2 ADC/2 DAC
• Thd Plus Noise: - 95 dB ADC / - 90 dB DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1501 - BOARD EVAL FOR CS4245 CODEC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1034

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4.3
High-Pass Filter and DC Offset Calibration
When using operational amplifiers in the input circuitry driving the CS4245, a small DC offset may be driven
into the A/D converter. The CS4245 includes a high-pass filter after the decimator to remove any DC offset
which could result in recording a DC level, possibly yielding clicks when switching between devices in a mul-
tichannel system.
The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation
filter. If the HPFFreeze bit (See
eration, the current value of the DC offset for the each channel is frozen and this DC offset will continue to
be subtracted from the conversion result. This feature makes it possible to perform a system DC offset cal-
ibration by:
1. Running the CS4245 with the high-pass filter enabled until the filter settles. See the ADC Digital Filter
2. Disabling the high-pass filter and freezing the stored DC offset.
A system calibration performed in this way will eliminate offsets anywhere in the signal path between the
calibration point and the CS4245.
derived from MCLK1. For more information on Synchronous and Asynchronous Modes, see
nous / Asynchronous Mode” on page
For each serial port, the serial bit clock must be equal to 128x, 64x, 48x or 32x Fs, depending on the de-
sired speed mode. If operating in Asynchronous Mode, the serial bit clock SCLK1 must be synchronously
derived from MCLK1 and SCLK2 must be synchronously derived from MCLK2. If operating in Synchro-
nous Mode, SCLK1, and SCLK2 must be synchronously derived from MCLK1. Refer to
quired serial bit clock to Left/Right clock ratios.
SCLK/LRCK Ratio
Characteristics section for filter settling time.
“ADC High-Pass Filter Freeze (Bit 1)” on page
Table 3. Slave Mode Serial Bit Clock Ratios
32x, 48x, 64x, 128x
30.
Single-Speed
Double-Speed
32x, 48x, 64x
44.) is set during normal op-
Quad-Speed
32x, 48x, 64x
Table 3
“Synchro-
CS4245
DS656F2
for re-