CS4245-CQZ Cirrus Logic Inc, CS4245-CQZ Datasheet - Page 41

IC CODEC AUD STER 104DB 48LQFP

CS4245-CQZ

Manufacturer Part Number
CS4245-CQZ
Description
IC CODEC AUD STER 104DB 48LQFP
Manufacturer
Cirrus Logic Inc
Type
Stereo Audior
Datasheet

Specifications of CS4245-CQZ

Package / Case
48-LQFP
Data Interface
Serial
Resolution (bits)
24 b
Number Of Adcs / Dacs
2 / 2
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
104 / 104
Voltage - Supply, Analog
3.13 V ~ 5.25 V
Voltage - Supply, Digital
3.13 V ~ 5.25 V
Operating Temperature
-10°C ~ 70°C
Mounting Type
Surface Mount
Number Of Adc Inputs
12
Number Of Dac Outputs
4
Conversion Rate
192 KSPS
Interface Type
Serial (I2C, SPI)
Resolution
24 bit
Operating Supply Voltage
3.3 V, 5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 10 C
Number Of Channels
2 ADC/2 DAC
Thd Plus Noise
- 95 dB ADC / - 90 dB DAC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1501 - BOARD EVAL FOR CS4245 CODEC
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1034

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DS656F2
6. REGISTER DESCRIPTION
6.1
6.2
6.2.1
6.2.2
6.2.3
PART3
Freeze
7
7
Chip ID - Register 01h
Function:
This register is Read-Only. Bits 7 through 4 are the part number ID, which is 1100b (0Ch), and the remaining
bits (3 through 0) indicate the device revision as shown in
Power Control - Address 02h
Freeze (Bit 7)
Function:
This function allows modifications to be made to certain control port bits without the changes taking effect
until the Freeze bit is disabled. To make multiple changes to these bits take effect simultaneously, set the
Freeze bit, make all changes, then clear the Freeze bit. The bits affected by the Freeze function are listed
in
Power-Down MIC (Bit 3)
Function:
The microphone preamplifier block will enter a low-power state whenever this bit is set.
Power-Down ADC (Bit 2)
Function:
The ADC pair will remain in a reset state whenever this bit is set.
Table
Reserved
PART2
5.
6
6
Reserved
PART1
MuteDAC
MuteADC
Gain[5:0]
Gain[5:0]
Vol[7:0]
Vol[7:0]
Name
5
5
REV[2:0]
001
010
011
Table 4. Device Revision
Table 5. Freeze-able Bits
Reserved
PART0
4
4
Register
0Ah
0Bh
03h
04h
07h
08h
PDN_MIC
REV3
3
3
Revision
Table 4
B, C0
C1
A
PDN_ADC
below.
REV2
2
2
Bit(s)
5:0
5:0
7:0
7:0
2
2
PDN_DAC
REV1
1
1
CS4245
REV0
PDN
0
0
41

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