CS42L51-CNZ Cirrus Logic Inc, CS42L51-CNZ Datasheet - Page 21

• Manufacturer Part Number: CS42L51-CNZ
• Description: IC CODEC STEREO W/HDPN AMP 32QFN
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS42L51-CNZ

• Package / Case: 32-QFP
• Data Interface: PCM Audio Interface
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 98 / 98
• Voltage - Supply, Analog: 1.8V, 2.5V
• Voltage - Supply, Digital: 1.8V, 2.5V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 6
• Number Of Dac Outputs: 2
• Conversion Rate: 96 KSPS
• Interface Type: Serial (2-Wire, 3-Wire, I2C, SPI)
• Resolution: 24 bit
• Operating Supply Voltage: 1.8 V / 2.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 2 ADC/2 DAC
• Thd Plus Noise: - 88 dB ADC / - 86 dB DAC
• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1005 - BOARD EVAL FOR CS42L51 CODEC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1045

DS679F1
Master Mode
Output Sample Rate (LRCK)
LRCK Duty Cycle
SCLK Frequency
SCLK Duty Cycle
LRCK Edge to SDOUT MSB Output Delay
SDOUT Setup Time Before SCLK Rising Edge
SDOUT Hold Time After SCLK Rising Edge
SDIN Setup Time Before SCLK Rising Edge
SDIN Hold Time After SCLK Rising Edge
14. After powering up the CS42L51, RESET should be held low after the power supplies and clocks are
15. See
16. See
17.
18. “MCLK” refers to the external master clock applied.
settled.
“Master” on page 39
(Note 17)
“Example System Clock Frequencies” on page 79
Parameters
Figure 5. Serial Audio Interface Master Mode Timing
Figure 4. Serial Audio Interface Slave Mode Timing
SDOUT
SDOUT
LRCK
LRCK
SCLK
SCLK
SDIN
SDIN
t
t
t
s(LK-SK)
d(MSB)
d(MSB)
t
t
s(SD-SK)
s(SD-SK)
All Speed Modes
MSB
MSB
MSB
MSB
//
//
//
//
//
//
//
//
//
//
//
//
//
//
t
t
h(SK-SDO)
h(SK-SDO)
t
t
h
h
(Note 17)
t
t
P
P
for typical MCLK frequencies.
//
//
t
t
Symbol
s(SDO-SK)
h(SK-SDO)
t
MSB-1
MSB-1
s(SD-SK)
MSB-1
MSB-1
t
t
t
d(MSB)
s(SDO-SK)
s(SDO-SK)
1/t
F
t
h
s
P
Min
45
45
20
30
20
20
-
-
-
MCLK
---------------- -
128
64•F
Max
55
55
52
-
-
-
-
CS42L51
s
Units
Hz
Hz
ns
ns
ns
ns
ns
%
%
21