CS42L51-CNZ Cirrus Logic Inc, CS42L51-CNZ Datasheet - Page 59

IC CODEC STEREO W/HDPN AMP 32QFN

CS42L51-CNZ

Manufacturer Part Number
CS42L51-CNZ
Description
IC CODEC STEREO W/HDPN AMP 32QFN
Manufacturer
Cirrus Logic Inc
Type
Stereo Audior
Datasheet

Specifications of CS42L51-CNZ

Package / Case
32-QFP
Data Interface
PCM Audio Interface
Resolution (bits)
24 b
Number Of Adcs / Dacs
2 / 2
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
98 / 98
Voltage - Supply, Analog
1.8V, 2.5V
Voltage - Supply, Digital
1.8V, 2.5V
Operating Temperature
-10°C ~ 70°C
Mounting Type
Surface Mount
Number Of Adc Inputs
6
Number Of Dac Outputs
2
Conversion Rate
96 KSPS
Interface Type
Serial (2-Wire, 3-Wire, I2C, SPI)
Resolution
24 bit
Operating Supply Voltage
1.8 V / 2.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 10 C
Number Of Channels
2 ADC/2 DAC
Thd Plus Noise
- 88 dB ADC / - 86 dB DAC
Peak Reflow Compatible (260 C)
No
Leaded Process Compatible
No
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1005 - BOARD EVAL FOR CS42L51 CODEC
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1045

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CS42L51
DAC Soft Ramp and Zero Cross Control (DAC_SZC[1:0])
Default = 10
00 - Immediate Change
01 - Zero Cross
10 - Soft Ramp
11 - Soft Ramp on Zero Crossings
Function:
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control
Immediate Change
When Immediate Change is selected all volume-level changes will take effect immediately in one step.
Zero Cross
This setting dictates that signal-level changes, either by gain changes, attenuation changes or muting, will
occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a
timeout period between 1024 and 2048 sample periods (21.3 ms to 42.7 ms at 48 kHz sample rate) if the
signal does not encounter a zero crossing. The zero cross function is independently monitored and imple-
mented for each channel. Note: The LIM_SRDIS bit is ignored.
Soft Ramp
Soft Ramp allows level changes, either by gain changes, attenuation changes or muting, to be implemented
by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 0.5 dB per 4
left/right clock periods.
Soft Ramp on Zero Crossing
This setting dictates that signal-level changes, either by gain changes, attenuation changes or muting, will
occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur
after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if
the signal does not encounter a zero crossing. The zero cross function is independently monitored and im-
plemented for each channel. Note: The LIM_SRDIS bit is ignored.
6.10
ALCX & PGAX Control: ALCA, PGAA (Address 0Ah) & ALCB, PGAB (Address 0Bh)
7
6
5
4
3
2
1
0
ALCX_SRDIS ALCX_ZCDIS
Reserved
PGAX_VOL4
PGAX_VOL3
PGAX_VOL2
PGAX_VOL1
PGAX_VOL0
ALCX Soft Ramp Disable (ALCX_SRDIS)
Default: 0
0 - Off
1 - On
Function:
Overrides the SOFTx bit setting for the ADC. When this bit is set, the ALC attack rate in the PGA will not be
dictated by the soft ramp setting. ALC volume-level changes will take effect in one step.
DS679F1
59

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