CS42L51-CNZ Cirrus Logic Inc, CS42L51-CNZ Datasheet - Page 56

• Manufacturer Part Number: CS42L51-CNZ
• Description: IC CODEC STEREO W/HDPN AMP 32QFN
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS42L51-CNZ

• Package / Case: 32-QFP
• Data Interface: PCM Audio Interface
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 98 / 98
• Voltage - Supply, Analog: 1.8V, 2.5V
• Voltage - Supply, Digital: 1.8V, 2.5V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 6
• Number Of Dac Outputs: 2
• Conversion Rate: 96 KSPS
• Interface Type: Serial (2-Wire, 3-Wire, I2C, SPI)
• Resolution: 24 bit
• Operating Supply Voltage: 1.8 V / 2.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 2 ADC/2 DAC
• Thd Plus Noise: - 88 dB ADC / - 86 dB DAC
• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1005 - BOARD EVAL FOR CS42L51 CODEC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1045

56
6.7
AINB_MUX1
7
ADCx Input Select, Invert & Mute (Address 07h)
ADCX Input Select Bits (AINX_MUX[1:0])
Default: 00
Function:
Selects the specified analog input signal into ADCx. The microphone pre-amplifier is only available when
PDN_PGAx is disabled. See
ADCX Invert Signal Polarity (INV_ADCX)
Default: 0
0 - Disabled
1 - Enabled
Function:
When enabled, this bit will invert the signal polarity of the ADC x channel.
ADCX Channel Mute (ADCX_MUTE)
Default: 0
0 - Disabled
1 - Enabled
Function:
The output of channel x ADC will mute when enabled. The muting function is affected by the ADCx Soft bit
(SOFT).
PDN_PGAx AINx_MUX[1:0]
0
0
0
0
1
1
1
1
AINB_MUX0
6
AIN3x / MICINx
AINA_MUX1
00
01
10
11
00
01
10
11
AIN1x
AIN2x
5
Figure
AIN1x-->PGAx
AIN2x-->PGAx
AIN3x/MICINx-->PGAx
AIN3x/MICINx-->Pre-Amp
AIN1x
AIN2x
AIN3x/MICINx
Reserved
Figure 26. AIN & PGA Selection
AINA_MUX0
26.
32 dB
+16/
AINx_MUX[1:0]
4
PDN_PGAx
MUX
Selected Path to ADC
INV_ADCB
3
(+16/+32 dB Gain)
Decoder
PGA
AIN1x
AIN2x
AIN3x
INV_ADCA
2
-->PGAx
MUX
ADCB_MUTE ADCA_MUTE
1
ADC
CS42L51
DS679F1
0