CS42L51-CNZ Cirrus Logic Inc, CS42L51-CNZ Datasheet - Page 53

IC CODEC STEREO W/HDPN AMP 32QFN

CS42L51-CNZ

Manufacturer Part Number
CS42L51-CNZ
Description
IC CODEC STEREO W/HDPN AMP 32QFN
Manufacturer
Cirrus Logic Inc
Type
Stereo Audior
Datasheet

Specifications of CS42L51-CNZ

Package / Case
32-QFP
Data Interface
PCM Audio Interface
Resolution (bits)
24 b
Number Of Adcs / Dacs
2 / 2
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
98 / 98
Voltage - Supply, Analog
1.8V, 2.5V
Voltage - Supply, Digital
1.8V, 2.5V
Operating Temperature
-10°C ~ 70°C
Mounting Type
Surface Mount
Number Of Adc Inputs
6
Number Of Dac Outputs
2
Conversion Rate
96 KSPS
Interface Type
Serial (2-Wire, 3-Wire, I2C, SPI)
Resolution
24 bit
Operating Supply Voltage
1.8 V / 2.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 10 C
Number Of Channels
2 ADC/2 DAC
Thd Plus Noise
- 88 dB ADC / - 86 dB DAC
Peak Reflow Compatible (260 C)
No
Leaded Process Compatible
No
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1005 - BOARD EVAL FOR CS42L51 CODEC
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1045

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DS679F1
6.5
ADC_SNGVOL
7
ADC I²S or Left-Justified (ADC_I²S/LJ)
Default: 0
0 - Left-Justified
1 - I²S
Function:
Selects either the I²S or Left-Justified digital interface format for the data on SDOUT. The required relation-
ship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and
the options are detailed in this section .
Digital Mix (DIGMIX)
Default: 0
Function:
Selects between the ADC or a digital mix of the ADC and DAC into the serial port to the SDOUT pin. This
mix function is affected by the data select bits DATA_SEL[1:0].
Microphone Mix (MICMIX)
Default: 0
0 - Disabled; No Mix: Left/Right Channel to ADC serial port, SDOUT.
1 - Enabled; Mix: Differential mix ((A-B)/2)to ADC serial port, SDOUT.
Function:
Selects between the ADC stereo mix or a differential mix of analog inputs A and B.
MIC Control (Address 05h)
ADC Single Volume Control (ADC_SNGVOL)
Default: 0
0 - Disabled
1 - Enabled
Function:
The individual PGA Volume (PGAx_VOLx) and ADC channel attenuation (ADCx_ATTx) levels as well as
the ALC A and B enable (ALC_ENx) are independently controlled by their respective control registers when
this function is disabled. When enabled, the volume on both channels is determined by the ADCA Attenuator
Control register, or the PGAA Control register, and the ADCB Attenuator and PGAB Control registers are
ignored. The ALC enable control for channel B is controlled by the ALC A enable when the ADC_SNGVOL
bit is enabled and the ALC_ENB control register is ignored.
DIGMIX
0
1
ADCB_DBOOST ADCA_DBOOST MICBIAS_SEL MICBIAS_LVL1 MICBIAS_LVL0
6
DATA_SEL[1:0]
00
01
10
xx
11
5
No Mix: ADC to ADC serial port, SDOUT data.
No Mix: SDIN data to ADC serial port, SDOUT data.
Mix: ADC + SDIN data to ADC serial port, SDOUT data.
No Mix: ADC to ADC serial port, SDOUT data.
Reserved
4
3
Mix Selected
2
MICB_BOOST MICA_BOOST
1
CS42L51
0
53

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