CS42324-CQZ Cirrus Logic Inc, CS42324-CQZ Datasheet - Page 31

• Manufacturer Part Number: CS42324-CQZ
• Description: IC CODEC STEREO AUDIO 48LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42324-CQZ

• Package / Case: 48-LQFP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 1 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 95 / 100
• Voltage - Supply, Analog: 3.13 V ~ 3.47 V
• Voltage - Supply, Digital: 3.13 V ~ 3.47 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 1
• Number Of Dac Outputs: 2
• Conversion Rate: 96 KSPS
• Interface Type: Serial (I2S, SPI)
• Resolution: 24 bit
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Channels: 1 ADC/2 DAC
• Supply Current: 10 mA to 24 mA
• Thd Plus Noise: - 88 dB ADC / - 90 dB DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1498 - BOARD EVAL FOR CS42324 CODEC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1602

DS721A6
4.2.3
4.2.4
Internal-MCLK1
Internal-MCLK2
Internal-LRCK1
Internal-LRCK2
Internal-SCLK1
Internal-SCLK2
SDOUT
ADC, DAC1, and DAC2 clock selection
The ADC, DAC1, and DAC2 can be independently set to use either of the two serial ports as a clock
source. Each also has control over which MCLK to use. This allows for full flexibility in configuration of the
converter. Master/Slave control is achieved at the serial port level (See
converters discussed here are always slave.
Each converter has a bit in the registers (xxx_SP, where xxx = ADC, DAC1, or DAC2) which allows se-
lection of the SCLK/LRCK pair used for the converter. The xxx_MCLK bits select which MCLK source to
use for the converter. If the serial port selected for use is in master mode, this selection must be the same
as the MCLK_SPx for the serial port which is in use. In Slave mode the MCLK selected must be synchro-
nous to the LRCK/SCLK selected by xxx_SP.
High-Impedance Digital Output
Each serial port may be placed on a clock/data bus that allows multiple masters, without the need for ex-
ternal buffers. The 3ST_SP1, 3ST_SP2 and 3ST_SDOUT bits place the internal buffers for the serial port
signals in a high-impedance state, allowing another device to transmit clocks or data without bus conten-
tion.
ADC_DIF[2:0]
ADC_MCLK
ADC_SP
0
1
0
1
0
1
Transm itting Device #1
ADC
CS42324
3ST_SDOUT
3ST_SPx
Figure 11. Converter Clocking
Figure 12. Tri-State Serial Port
Internal-MCLK1
Internal-MCLK2
Internal-LRCK1
Internal-LRCK2
Internal-SCLK1
Internal-SCLK2
SDIN1
SCLKx/LRCKx
Receiving Device
SDOUT
DAC1_DIF[2:0]
DAC1_MCLK
DAC1_SP
0
1
0
1
0
1
DAC1
Transm itting Device #2
Internal-MCLK1
Internal-MCLK2
Internal-LRCK1
Internal-LRCK2
Internal-SCLK1
Internal-SCLK2
Figure 9 on page
SDIN2
DAC2_DIF[2:0]
DAC2_MCLK
DAC2_SP
0
1
0
1
0
1
29); the internal
CS42324
DAC2
31