CS42324-CQZ Cirrus Logic Inc, CS42324-CQZ Datasheet - Page 48

• Manufacturer Part Number: CS42324-CQZ
• Description: IC CODEC STEREO AUDIO 48LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42324-CQZ

• Package / Case: 48-LQFP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 1 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 95 / 100
• Voltage - Supply, Analog: 3.13 V ~ 3.47 V
• Voltage - Supply, Digital: 3.13 V ~ 3.47 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 1
• Number Of Dac Outputs: 2
• Conversion Rate: 96 KSPS
• Interface Type: Serial (I2S, SPI)
• Resolution: 24 bit
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Channels: 1 ADC/2 DAC
• Supply Current: 10 mA to 24 mA
• Thd Plus Noise: - 88 dB ADC / - 90 dB DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1498 - BOARD EVAL FOR CS42324 CODEC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1602

48
6.3.2
6.3.3
6.3.4
6.3.5
INT Pin High/Low Active (INT_H/L)
When this bit is set, the INT pin will function as an active high CMOS driver. When this bit is cleared, the
INT pin will function as an active low open drain driver and will require an external pull-up resistor for prop-
er operation.
Freeze
This function allows modifications to be made to certain bits without the changes taking effect until the
Freeze bit is disabled. To make multiple changes to these bits take effect simultaneously, set the Freeze
bit, make all changes, then clear the Freeze bit. The bits affected by the Freeze function are listed in
Table
Tri-State SDOUT
When this bit is set, SDOUT will be placed in a high-impedance state.
Tri-State Serial Port 1
When enabled, and the device is configured as a master, then SCLK1 and LRCK1 of Serial Port 1 (SP1)
will be placed in a high-impedance output state. If Serial Port 1 is configured as a slave, SCLK1 and
LRCK1 will remain as inputs.
0
1
0
1
0
1
0
1
TRI-SDOUT
FREEZE
TRI-SP1
INT_H/L
10.
DAC1 Ch A Vol. Control
DAC1 Ch B Vol. Control
DAC2 Ch A Vol. Control
DAC2 Ch B Vol. Control
Active low, open drain driver
Active high, CMOS driver
Changes to registers take effect immediately
Changes to registers are held until FREEZE is released
Output
High-impedance
SCLK1 and LRCK1 operate as inputs if Serial Port 1 is configured as a slave; SCLK1 and LRCK1
operate as outputs if Serial Port 1 is configured as a master
SCLK1 and LRCK1 operate as inputs if Serial Port 1 is configured as a slave; SCLK1 and LRCK1
become high-impedance outputs if Serial Port 1 is configured as a master
ADC Ch A Vol. Control
ADC Ch B Vol. Control
Mute Control
Name
Table 10. Freeze-able Bits
Register
SCLK1 and LRCK1 State
01h
0Fh
10h
11h
12h
13h
14h
INT Pin Polarity
FREEZE Status
SDOUT state
Bit(s)
7:0
7:0
7:0
7:0
7:0
7:0
7:0
CS42324
DS721A6