CS42324-CQZ Cirrus Logic Inc, CS42324-CQZ Datasheet - Page 40

• Manufacturer Part Number: CS42324-CQZ
• Description: IC CODEC STEREO AUDIO 48LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42324-CQZ

• Package / Case: 48-LQFP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 1 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 95 / 100
• Voltage - Supply, Analog: 3.13 V ~ 3.47 V
• Voltage - Supply, Digital: 3.13 V ~ 3.47 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 1
• Number Of Dac Outputs: 2
• Conversion Rate: 96 KSPS
• Interface Type: Serial (I2S, SPI)
• Resolution: 24 bit
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Channels: 1 ADC/2 DAC
• Supply Current: 10 mA to 24 mA
• Thd Plus Noise: - 88 dB ADC / - 90 dB DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1498 - BOARD EVAL FOR CS42324 CODEC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1602

40
4.6
4.6.1
Device Control
In Software Mode, all functions and features may be controlled either by two-wire I²C or SPI Software Mode
interface. In Hardware Mode, a limited feature set may be controlled via hardware control pins.
Hardware Mode
A limited feature-set is available when the CS42324 powers up in Hardware Mode (see
Power-Up Sequence, Hardware Mode” on page
Table 9
available.
Power Control
SP_ERROR
Auto Detect
Serial Port Master/Slave and Speed Mode
Async / Sync Mode
MCLK Divide
Serial Port Interface Format
Freeze Bit Settings
ADC Volume & Gain
ADC High-Pass Filter
ADC High-Pass Filter Freeze
AIN Input Select to ADC
DAC1 & DAC2 Volume & Gain
DAC1 & DAC2 De-Emphasis
AOUT1x
AOUT2x
AOUT3x
AOUTxx
shows a list of functions/features, the default configuration and the associated hardware control
Feature/Function
(SDOUT source)
Table 9. Hardware Mode Feature Summary
Serial Port 1
Serial Port 2
Zero Cross
Zero Cross
Soft Ramp
Soft Ramp
Hardware Mode Feature Summary
Volume
Volume
source
source
source
MUTE
DAC1
DAC2
Invert
Invert
Mixer
Mute
Mute
ADC
(256x/128xFs, 512x/256xFs only)
Enabled; Active low, open drain
Continuous DC Subtraction
38) and may be controlled via hardware control pins.
Default Configuration
Synchronous only
Output of DAC1
Output of DAC2
Disabled (‘00’)
Powered Up
Powered Up
Powered Up
(Selectable)
(Selectable)
(Selectable)
(Selectable)
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
AIN1x
AIN1
0 dB
0 dB
“M0” and “M1”, pins 1 and 2
Hardware Control
(see
(see
(see
(see
“MDIV” pin 3
MUTE pin 4
“DIF” pin 5
“Recommended
page
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page
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CS42324
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DS721A6