CS42324-CQZ Cirrus Logic Inc, CS42324-CQZ Datasheet - Page 62

• Manufacturer Part Number: CS42324-CQZ
• Description: IC CODEC STEREO AUDIO 48LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42324-CQZ

• Package / Case: 48-LQFP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 1 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 95 / 100
• Voltage - Supply, Analog: 3.13 V ~ 3.47 V
• Voltage - Supply, Digital: 3.13 V ~ 3.47 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 1
• Number Of Dac Outputs: 2
• Conversion Rate: 96 KSPS
• Interface Type: Serial (I2S, SPI)
• Resolution: 24 bit
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Channels: 1 ADC/2 DAC
• Supply Current: 10 mA to 24 mA
• Thd Plus Noise: - 88 dB ADC / - 90 dB DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1498 - BOARD EVAL FOR CS42324 CODEC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1602

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6.20.3 DAC1 Auto Mute Left Interrupt Status (DAC1_AMUTEL)
6.20.4 DAC1 Auto Mute Right Interrupt Status (DAC1_AMUTEL)
6.20.5 Serial Port 2 Clock Error Interrupt Status (SP2_CLKERR)
6.20.6 Serial Port 1 Clock Error Interrupt Status (SP1_CLKERR)
6.20.7 ADC Positive Overflow Interrupt Bit (ADC_OVFLP)
This bit is read only. When set, indicates that DAC1 left channel has had an auto-mute condition since the
last read of this register. Conditions which cause an auto-mute, such as receiving 4096 consecutive sam-
ples of zeroes or ones on the left channel of SDIN1, will cause this bit to be set. This interrupt status bit
is an edge-triggered event and will be cleared following a read of this register.
The INT pin will go active according to the DAC_AMUTE[1:0] bits in the
on page 59
This bit is read only. When set, indicates that DAC1 right channel has had an auto-mute condition since
the last read of this register. Conditions which cause an auto-mute, such as receiving 4096 consecutive
samples of zeroes or ones on the right channel of SDIN1, will cause this bit to be set. This interrupt status
bit is an edge-triggered event and will be cleared following a read of this register.
The INT pin will go active according to the DAC_AMUTE[1:0] bits in the
on page 59
This bit is read only. When set, indicates that Serial Port 2 has had a clock error since the last read of this
register. Conditions which cause a clock error in the serial port, such as loss of LRCK2, SCLK2, an
MCLKx/LRCK2 ratio change, or speed mode change, will cause this bit to be set. This interrupt bit is an
edge-triggered event and will be cleared following a read of this register.
The INT pin will go active according to the SP2_CLKERR[1:0] bits in the
on page 59
This bit is read only. When set, indicates that Serial Port 1 has had a clock error since the last read of this
register. Conditions which cause a clock error in the serial port, such as loss of LRCK1, SCLK1, an
MCLKx/LRCK1 ratio change, or speed mode change, will cause this bit to be set. This interrupt bit is an
edge-triggered event and will be cleared following a read of this register.
The INT pin will go active according to the SP1_CLKERR[1:0] bits in the
on page 59
This bit is read only. When set, indicates that a positive over-range condition occurred anywhere in the
CS42324 ADC signal path and has ADC data has been clipped to positive full scale since the last read of
this register. This interrupt bit is an edge-triggered event and will be cleared following a read of this reg-
ister.
The INT pin will go active according to the ADC_OVFLx[1:0] bits in the
page 59
of the ADC use the OVFL pin.
and the status of this bit if ADC_OVFLPM bit is cleared. To determine the current overflow state
and the status of this bit if DAC1_AMUTELM bit is cleared.
and the status of this bit if DAC1_AMUTERM bit is cleared.
and the status of this bit if SP2_CLKERRM bit is cleared.
and the status of this bit if SP1_CLKERRM bit is cleared.
“Interrupt Mode (Address 16h)” on
“Interrupt Mode (Address 16h)”
“Interrupt Mode (Address 16h)”
“Interrupt Mode (Address 16h)”
“Interrupt Mode (Address 16h)”
CS42324
DS721A6