CS42324-CQZ Cirrus Logic Inc, CS42324-CQZ Datasheet - Page 32

• Manufacturer Part Number: CS42324-CQZ
• Description: IC CODEC STEREO AUDIO 48LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42324-CQZ

• Package / Case: 48-LQFP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 1 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 95 / 100
• Voltage - Supply, Analog: 3.13 V ~ 3.47 V
• Voltage - Supply, Digital: 3.13 V ~ 3.47 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 1
• Number Of Dac Outputs: 2
• Conversion Rate: 96 KSPS
• Interface Type: Serial (I2S, SPI)
• Resolution: 24 bit
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Channels: 1 ADC/2 DAC
• Supply Current: 10 mA to 24 mA
• Thd Plus Noise: - 88 dB ADC / - 90 dB DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1498 - BOARD EVAL FOR CS42324 CODEC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1602

32
4.2.5
4.2.6
SDIN1/2
SDIN1/2
SDOUT
SDOUT
LRCKx
SCLKx
SCLKx
LRCKx
SDIN1/2
SDOUT
LRCKx
SCLKx
Digital Interface Formats
Each converter (ADC, DAC1, and DAC2) has independent selection for serial formats (I²S, Left-Justified,
etc.). Data is clocked out of the ADC or into the DAC on the rising edge of SCLK.
the general structure of each format. Refer to
“Switching Characteristics - Serial Audio (Cont.)” on page 23
and data. For a complete overview of Serial Audio Interface Formats, please reference Application Note
AN282.
Synchronization of Multiple Devices
In systems where multiple ADCs and DACs are required, care must be taken to achieve simultaneous
sampling. To ensure synchronous sampling, the master clocks and left/right clocks must be the same for
all of the CS42324’s in the system. If only one master clock source is needed, one solution is to place one
CS42324 in Master Mode, and slave all of the other devices to the one master.
LO
HI
M S B
DIF (Pin 5) Setting
M S B
Figure 15. Right-Justified 16-Bit Data, Right-Justified 24-Bit Data
AOUTxA
AOUTxA
L eft C h a n n el
L eft C h a n n el
AINxA
AINxA
AOUTxA
L e ft C h a n n e l
AINxA
Figure 13. Left-Justified up to 24-Bit Data
M S B
Table 8. Hardware Mode Interface Format Control
Left-Justified Interface
I²S Interface
Figure 14. I²S up to 24-Bit Data
L S B
L S B
L S B
“Switching Characteristics - Serial Audio” on page 22
M S B
M S B
for exact timing relationship between clocks
Selection
Rig ht C h a n n el
Rig ht C h a n n el
AOUTxB
AOUTxB
AINxB
AINxB
R i g h t C h a n n e l
AOUTxB
AINxB
M S B
Figures 13-17
L S B
L S B
CS42324
L S B
MSB
DS721A6
illustrate
MSB
or