ADAU1381BCPZ Analog Devices Inc, ADAU1381BCPZ Datasheet - Page 48

• Manufacturer Part Number: ADAU1381BCPZ
• Description: IC AUDIO CODEC STEREO LN 32LFCSP
• Manufacturer: Analog Devices Inc
• Type: Stereo Audior

Specifications of ADAU1381BCPZ

• Data Interface: Serial, SPI™
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• S/n Ratio, Adcs / Dacs (db) Typ: 97 / 100
• Dynamic Range, Adcs / Dacs (db) Typ: 96.5 / 100
• Voltage - Supply, Analog: 1.8 V ~ 3.65 V
• Voltage - Supply, Digital: 1.63 V ~ 3.65 V
• Operating Temperature: -25°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN, CSP Exposed Pad
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 3
• No. Of Output Channels: 3
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 100dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADAU1381
RECORD PATH CONFIGURATION
Register 16392 (0x4008), Digital Microphone and
Analog Beep Control
This register controls the digital microphone settings and the
analog beep input gain.
Bits[5:4], Digital Microphone Enable
These bits control the enable function for the stereo digital
microphones. The analog front end is powered down when
using a digital microphone.
Table 35. Digital Microphone and Analog Beep Control Register
Bits
[7:6]
[5:4]
3
[2:0]
Description
Reserved
Digital microphone enable
00: disabled
01: MICD1 enabled
10: MICD2 enabled
11: reserved
Beep input mute
0: muted
1: unmuted
Beep input gain. Note that Setting 100 sets the input beep gain to −23 dB.
000: 0 dB
001: +6 dB
010: +10 dB
011: +14 dB
100: −23 dB
101: +20 dB
110: +26 dB
111: +32 dB
Rev. B | Page 48 of 84
Bit 3, Beep Input Mute
This bit mutes the beep input.
Bits[2:0], Beep Input Gain
This bit controls the gain setting for the analog beep input; it
defaults at 0 dB and can be set as high as 32 dB. The beep signal
must be enabled in Register 16400 (0x4010), microphone bias
control and beep enable.
Default
00
0
000