ADAU1381BCPZ Analog Devices Inc, ADAU1381BCPZ Datasheet - Page 83

IC AUDIO CODEC STEREO LN 32LFCSP

ADAU1381BCPZ

Manufacturer Part Number
ADAU1381BCPZ
Description
IC AUDIO CODEC STEREO LN 32LFCSP
Manufacturer
Analog Devices Inc
Type
Stereo Audior
Datasheet

Specifications of ADAU1381BCPZ

Data Interface
Serial, SPI™
Resolution (bits)
24 b
Number Of Adcs / Dacs
2 / 2
Sigma Delta
No
S/n Ratio, Adcs / Dacs (db) Typ
97 / 100
Dynamic Range, Adcs / Dacs (db) Typ
96.5 / 100
Voltage - Supply, Analog
1.8 V ~ 3.65 V
Voltage - Supply, Digital
1.63 V ~ 3.65 V
Operating Temperature
-25°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-VFQFN, CSP Exposed Pad
Audio Codec Type
Stereo
No. Of Adcs
2
No. Of Dacs
2
No. Of Input Channels
3
No. Of Output Channels
3
Adc / Dac Resolution
24bit
Adcs / Dacs Signal To Noise Ratio
100dB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Register 16628 (0x40F4), Serial Data/GPIO Pin
Configuration
Bits[3:0], GPIO[0:3]
The serial data/GPIO pin configuration register controls the
functionality of the serial data port pins. If the bits in this
register are set to 1, then the GPIO[0:3] pins become GPIO
interfaces to the sound engine. If these bits are set to 0, they
remain LRCLK, BCLK, or serial port data pins, respectively.
Register 16630 (0x40F6), Sound Engine Run
Bit 0, Sound Engine Run
This bit, in conjunction with the sound engine frame rate, initiates
audio processing in the sound engine. When this bit is enabled,
the program counter begins to increment when a new frame of
audio data is input to the sound engine. When this bit is disabled,
the sound engine goes into standby mode.
Table 74. Serial Data/GPIO Pin Configuration Register
Bits
[7:4]
3
2
1
0
Table 75. Sound Engine Run Register
Bits
[7:1]
0
Table 76. Serial Port Sampling Rate Register
Bits
[7:3]
[2:0]
Description
Reserved
Sound engine run
0: sound engine standby
1: run the sound engine
Description
Reserved
Serial port control sampling rate
000: f
001: f
010: f
011: f
100: f
101: f
110: f
111: reserved
Description
Reserved
GPIO0
0: LRCLK
1: GPIO enabled
GPIO1
0: BCLK
1: GPIO enabled
GPIO2
0: serial data output
1: GPIO enabled
GPIO3
0: serial data input
1: GPIO enabled
S
S
S
S
S
S
S
/1 (48 kHz)
/6 (8 kHz)
/4 (12 kHz)
/3 (16 kHz)
/2 (24 kHz)
/1.5 (32 kHz)
/0.5 (96 kHz)
Rev. B | Page 83 of 84
Before going into standby mode, the following sequence must
be performed:
1.
2.
3.
When reenabling the sound engine run bit, the following
sequence must be followed:
1.
2.
Register 16632 (0x40F8), Serial Port Sampling Rate
Bits[2:0], Serial Port Control Sampling Rate
These bits set the serial port sampling rate as a function of the
audio sampling rate, f
sampling rate, sound engine sampling rate, and ADC and DAC
sampling rates should be equal.
Set the sound engine frame rate in Register 16619 to
0x7F (none).
Wait 3 ms.
Set the sound engine run bit in Register 16630 to 0x00.
Set the sound engine frame rate in Register 16619 to an
appropriate value.
Set the sound engine run bit in Register 16630 to 0x01.
S
. In most applications, the serial port
Default
0
0
0
0
Default
0
Default
000
ADAU1381

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