STLC5046 STMicroelectronics, STLC5046 Datasheet - Page 33

IC CODEC/FLTR PROG QUAD 64-TQFP

STLC5046

Manufacturer Part Number
STLC5046
Description
IC CODEC/FLTR PROG QUAD 64-TQFP
Manufacturer
STMicroelectronics
Type
PCM Codec/Filterr
Datasheets

Specifications of STLC5046

Data Interface
PCM Audio Interface
Resolution (bits)
16 b
Number Of Adcs / Dacs
4 / 4
Sigma Delta
Yes
Voltage - Supply, Analog
3.3 V ~ 5 V
Voltage - Supply, Digital
3.3 V ~ 5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
497-3665

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STLC5046
3.1.23
3.1.24
EN3=0: Disable reception of selected time slot.
EN3=1: Selected receive time slot on DR input is PCM decoded and transferred to VFRO1
output.
R36..0:Define receive time slot number (0 to 127) on carrying the PCM signal to be decoded
and transferred to VFRO2 output.If linear mode is selected (LIN=1 of CONF register) the 16
bits will be used as linear code as follows: the 8most significative bits in the programmed
time slot, the 8 least significative bits in the following timeslot.
Example: if R36..R30=00:
Pin-strap value (value 80h):
Referred to FS3.
PCM Shift register (PCMSH)
Addr=1Bh; Reset Value=00h
XS2..0:Effective start of the TX frame is the programmed values of clock pulses (0 to 7) after
the FS rising edge.
RS2..0:Effective start of the RX frame is the programmed values of clock pulses (0 to 7)
after the FS rising edge.
Pin-strap value (value=00h):
Interrupt Mask register for I/O port (DMASK)
Addr=1Ch; Reset Value=FFh
Addr=1Dh; Reset Value=XFh
15
Bit7
Bit7
1
0
14
13
Bit6
Bit6
XS2
0
0
12
TS0
11
Bit5
Bit5
XS1
0
0
10
Doc ID 7052 Rev 5
9
Bit4
XS0
Bit4
0
0
8
7
Bit3
Bit3
0
0
6
5
Bit2
Bit2
RS2
0
0
4
TS1
Registers addresses
3
RS1
Bit1
Bit1
0
0
2
1
Bit0
RS0
Bit0
0
0
33/51
0

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