STLC5046 STMicroelectronics, STLC5046 Datasheet - Page 8

• Manufacturer Part Number: STLC5046
• Description: IC CODEC/FLTR PROG QUAD 64-TQFP
• Manufacturer: STMicroelectronics
• Type: PCM Codec/Filterr

Specifications of STLC5046

• Data Interface: PCM Audio Interface
• Resolution (bits): 16 b
• Number Of Adcs / Dacs: 4 / 4
• Sigma Delta: Yes
• Voltage - Supply, Analog: 3.3 V ~ 5 V
• Voltage - Supply, Digital: 3.3 V ~ 5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-3665

Block diagram and pin connection
Table 3.
8/51
Not connected
Digital
Digital (dual mode)
15, 16,
17, 18,
32, 34,
47, 49,
1,2,63
41
64
27
54
13
12
11
10
61
60
59
58
57
N.
MCLK
Name
IO10
IO11
SUB
N.C.
RES
TSX
IO7
IO8
IO9
M0
M1
DX
DR
Pin description (continued)
Type
ODO
DPS
DTO
DIO
DIO
DIO
DIO
DIO
DI
DI
DI
DI
Substrate connection. Must be shorted together with VEE and VSS pins as close as
possible the chip.
Not connected.
Reserved: must be left not connected.
Mode select, see M1
Master clock input. Four possible frequencies can be used: 1.536/1.544 MHz;
2.048 MHz; 4.096 MHz; 8.192 MHz. The device automatically detect the frequency
applied. This signal is also used as bit clock and it is used to shift data into and out
of the DR and DX pins.
Transmit time slot (open drain output, 3.2mA). Normally it is floating in high
impedance state except when a time slot is active on the DX output. In this case
TSX output pulls low to enable the backplane line driver.
Transmit PCM interface. It remains in high impedance state except during the
assigned time slots during which the PCM data byte is shifted out on the rising edge
of MCLK.
Receive PCM interface. It remains inactive except during the assigned receive time
slots during which the PCM data byte is shifted in on the falling edge of MCLK.
SLIC control I/O pin #7. Can be programmed as input or output via DIR register.
Depending on content of CONF register can be a static input/output or a dynamic
input/output synchronized with the CSn output signals controlling the SLICs.
SLIC control I/O pin #8. (see IO7 description).
SLIC control I/O pin #9. (see IO7 description).
SLIC control I/O pin #10. (see IO7 description).
SLIC control I/O pin #11. (see IO7 description).
M1
0
1
0
1
M0
1
0
0
1
Doc ID 7052 Rev 5
Pin-strap mode: basic functions selected by proper pin strapping
MCU mode: device controlled via serial interface
Reset status
Not allowed
Function
Mode select
STLC5046