STLC5046 STMicroelectronics, STLC5046 Datasheet - Page 9

• Manufacturer Part Number: STLC5046
• Description: IC CODEC/FLTR PROG QUAD 64-TQFP
• Manufacturer: STMicroelectronics
• Type: PCM Codec/Filterr

Specifications of STLC5046

• Data Interface: PCM Audio Interface
• Resolution (bits): 16 b
• Number Of Adcs / Dacs: 4 / 4
• Sigma Delta: Yes
• Voltage - Supply, Analog: 3.3 V ~ 5 V
• Voltage - Supply, Digital: 3.3 V ~ 5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-3665

STLC5046
Table 3.
14
19
20
21
22
23
24
N.
IO0/GR2
IO2/GR3
IO1/PD2
IO3/PD3
IO4/FS1
IO5/FS2
FS/FS0
Name
Pin description (continued)
DIO/DI
DIO/DI
DIO/DI
DIO/DI
DIO/DI
DIO/DI
Type
DI
MCU control mode: FS.
Frame Sync. Pulse. A pulse or a square wave waveform with an 8kHz repetition
rate is applied to this pin to define the start of the receive and transmit frame.
Effective start of the frame can be then shifted of up to 7 clock pulses independently
in receive and transmit directions by proper programming of the PCMSH register.
Pin-strap control mode: FS0.
Frame Sync. pulse of channel #0. One MCLK cycle long, starts PCM data transfer
in the Time Slot following its falling edge (Short Frame Delayed Timing).
MCU control mode: IO0.
Slic control I/O pin #0. Can be programmed as input or output via DIR register.
Depending on content of CONF register can be a static input/output or a dynamic
input/output synchronized with the CSn output signals controlling the SLICs.
Pin-strap control mode: GR2.
Receive gain programming channel 2:
1: Receive gain = -0.8 dB
0: Rec. gain = -4.3 dB
MCU control mode: IO1.
Slic control I/O pin #1. (see IO0 description).
Pin-strap control mode: PD2.
Power Down command channel 2:
1: Channel 2 Codec is in power down.
(equivalent to CONF reg bit2 = 1)
0: Channel 2 Codec is in power up.
(equivalent to CONF reg. bit2 = 0)
MCU control mode: IO2.
Slic control I/O pin #2. (see IO0 description)
Pin-strap control mode: GR3.
Receive gain programming channel 3. (see GR2 description)
MCU control mode: IO3.
Slic control I/O pin #3. (see IO0 description).
Pin-strap control mode: PD3.
Power down command channel 3. (see PD2 description)
MCU control mode: IO4
Slic control I/O pin #4. (see IO0 description).
Pin-strap control mode: FS1.
Frame sync. pulse of channel #1. One MCLK cycle long, starts PCM data transfer in
the time slot following its falling edge (short frame delayed timing).
MCU control mode: IO4.
Slic control I/O pin #5. (see IO0 description).
Pin-strap control mode: FS2.
Frame sync. pulse of channel #1. One MCLK cycle long, starts PCM data transfer in
the time slot following its falling edge (short frame delayed timing).
Doc ID 7052 Rev 5
Function
Block diagram and pin connection
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