STLC5048TR STMicroelectronics, STLC5048TR Datasheet - Page 13

• Manufacturer Part Number: STLC5048TR
• Description: IC CODEC/FILTER PROGR 4CH 64TQFP
• Manufacturer: STMicroelectronics
• Type: PCM Codec/Filterr

Specifications of STLC5048TR

• Data Interface: PCM Audio Interface
• Resolution (bits): 16 b
• Number Of Adcs / Dacs: 4 / 4
• Sigma Delta: Yes
• Voltage - Supply, Analog: 3.3 V ~ 5 V
• Voltage - Supply, Digital: 3.3 V ~ 5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STLC5048
Table 5.
Not connected
2, 18, 63, 1
32, 64
No.
17
15
16
4
7
6
5
3
Pin descriptions (continued)
Name
CCLK
TSXB
DRB
DXB
N.C.
RES
INT
CO
CS
CI
Type
ODO
ODO
DTO
DI
DI
DI
DI
DI
Chip select input, when this pin is low control information can be written to or
read from the device via the CI and CO pins.
Clock of serial control bus. this clock shifts serial control information into or out
of CI or CO when CS input is low depending on the current instruction. CCLK
may be asynchronous with the other system clocks.
Control data input of serial control bus.
Control data is shifted in the device when CS is low and clocked by CCLK.
Depending on the addressed register different numbers of consecutive bytes
can be loaded.
Control data output of serial control bus.
Control data is shifted out the device when CS is low and clocked by CCLK.
Depending on the addressed register different numbers of consecutive bytes
can be shifted out.
Interrupt output (open drain), goes low when a data change has been detected
in the I/O pins or another interrupt source is active. One mask register allows to
mask any I/O pin. Interrupt is reset when the I/O register is read.
Transmit time slot (open drain output, 3.2 mA). Normally it is floating in high
impedance state except when a time slot is active on the DXB output. In this
case TSXB output pulls low to enable the backplane line driver.
Transmit PCM interface B. It remains in high impedance state except during the
assigned time slots during which the PCM data byte is shifted out on the rising
edge of MCLK.
Receive PCM interface B. It remains inactive except during the assigned
receive time slots during which the PCM data byte is shifted in on the falling
edge of MCLK.
Not connected, must be left open
Reserved pins, must be connected to ground
Description
Pin assignments and descriptions
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