STLC5048TR STMicroelectronics, STLC5048TR Datasheet - Page 27

• Manufacturer Part Number: STLC5048TR
• Description: IC CODEC/FILTER PROGR 4CH 64TQFP
• Manufacturer: STMicroelectronics
• Type: PCM Codec/Filterr

Specifications of STLC5048TR

• Data Interface: PCM Audio Interface
• Resolution (bits): 16 b
• Number Of Adcs / Dacs: 4 / 4
• Sigma Delta: Yes
• Voltage - Supply, Analog: 3.3 V ~ 5 V
• Voltage - Supply, Digital: 3.3 V ~ 5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STLC5048
5.7
TA7..0 and TB7..0, contents of PCHKA and PCHKB registers, define the minimum duration
of input A and B to generate interrupt; spurious transitions shorter than the programmed
value are ignored.
The time width can be calculated according to the formula:
Time - Width A = (TA7..0)*64μs
Time - Width B = (TB7..0)*64μs
If PCHKA/B is programmed to 00h the persistency check is not performed and any detected
transition will generate interrupt.
All the inputs, with or without persistency check, are sampled with a repetition rate of 32 μs.
Interrupt register (INT)
Addr=10h; reset value=00h
Read-only
Table 25.
In dynamic I/O configuration the ID3..0 bits latch the interrupt request from the related
channel (SLIC). Any single bit IDn is cleared after reading related I/O register or by setting
MCn bit high (that is, when channel n is disabled to generate interrupt).
In static I/O configuration ID0 and ID2 bits latch the interrupt request from I/O11..0 and
CS3..0 respectively:
●
●
●
●
●
●
●
The INT register is cleared after reading operation only if signals (alarm cause) are inactive.
Bit7
ID0: is set High when the interrupt is requested from any the I/O11..0 lines.
ID2: is set High when the interrupt is requested from any the CS3..0 (configured as
I/O).
ID0 and ID2 are cleared after reading related I/O register.
ID1 and ID3 are don’t care.
ITV = 1: If the interrupt has been generated by time-out violation on the MCU serial
interface.
IPCM = 1: When transmit PCM data reading/writing test is enabled an interrupt is
generated every time valid data are available (RRD bit set to 1) or must be written
(WRD bit set to 1). The interrupt is cleared after reading/writing the data in the
PCMRD/PCMWD register via the MCU interface.
ICKF = 1: If the interrupt has been generated by a clock failure on PCM port (MCLK).
1
Interrupt register (INT) bits
Bit6
ITV
0
IPCM
Bit5
0
ICKF
Bit4
1
Bit3
ID3
0
Bit2
ID2
0
Register description
Bit1
ID1
0
Bit0
ID0
0
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