STLC5048TR STMicroelectronics, STLC5048TR Datasheet - Page 38

IC CODEC/FILTER PROGR 4CH 64TQFP

STLC5048TR

Manufacturer Part Number
STLC5048TR
Description
IC CODEC/FILTER PROGR 4CH 64TQFP
Manufacturer
STMicroelectronics
Type
PCM Codec/Filterr
Datasheets

Specifications of STLC5048TR

Data Interface
PCM Audio Interface
Resolution (bits)
16 b
Number Of Adcs / Dacs
4 / 4
Sigma Delta
Yes
Voltage - Supply, Analog
3.3 V ~ 5 V
Voltage - Supply, Digital
3.3 V ~ 5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
STLC5048TR
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
STLC5048TR
Manufacturer:
ST
0
Register description
5.27
38/64
If linear mode is selected (LIN=1 of CONF register) the 16 bits will be carried out as follows:
the 8 most significant bits in the programmed time slot, the 8 least significant bits in the
following time slot.
Example: if T36..T30=00:
Table 52.
Receive time slot ch #0 (DRTS0)
Addr=56h; reset value=00h
Table 53.
Example: if R06..R00=00:
Table 54.
15
15
R/W
EN0
Bit7
EN0=0: Disable reception of selected time slot.
EN0=1: Selected receive time slot on DR input is PCM decoded and transferred to
VFRO0 output.
R06..0: Define receive time slot number (0 to 127) on carrying the PCM signal to be
decoded and transferred to VFRO0 output. If linear mode is selected (LIN=1 of CONF
register) the 16 bits will be used as linear code as follows: the 8 most significant bits in
the programmed time slot, the 8 least significant bits in the following time slot.
14
14
Transmit time slot ch #3 (DXTS3) time slots in linear mode
Receive time slot ch #0 (DRTS0) bits
Receive time slot ch #0 (DRTS0) time slots in linear mode
13
13
Bit6
R06
1
12
12
TS0
TS0
11
11
Bit5
R05
0
10
10
9
9
Bit4
R04
1
8
8
6
6
Bit3
R03
0
5
5
4
4
Bit2
R02
1
3
3
TS1
TS1
7
7
Bit1
R01
1
2
2
STLC5048
1
1
Bit0
R00
0
0
0

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