STLC5048TR STMicroelectronics, STLC5048TR Datasheet - Page 25

• Manufacturer Part Number: STLC5048TR
• Description: IC CODEC/FILTER PROGR 4CH 64TQFP
• Manufacturer: STMicroelectronics
• Type: PCM Codec/Filterr

Specifications of STLC5048TR

• Data Interface: PCM Audio Interface
• Resolution (bits): 16 b
• Number Of Adcs / Dacs: 4 / 4
• Sigma Delta: Yes
• Voltage - Supply, Analog: 3.3 V ~ 5 V
• Voltage - Supply, Digital: 3.3 V ~ 5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STLC5048
5.4
5.5
CIO0..3=0 The CS0..3 is a static input, DATA is written in DATA2 register bits 0..3.
CIO0..3=1 The CS0..3 is a static output, DATA is taken from DATA2 register bits 0..3.
I/O data register channel #2 (DATA2)
Addr=06h; reset value=00h
Addr=07h; reset value=X0h
If bit 4 of CONF register (STA)=0 dynamic I/O mode:
Table 17.
Table 18.
When CS2 is active D211..0 are transferred to the corresponding I/O pins configured as
outputs (see DIR register). For the I/O pins configured as inputs the corresponding D211..0
will be written by the values applied to those pins while CS2 is low.
If bit 4 of CONF register (STA)=1 static I/O mode:
Table 19.
CD0..3 are transferred to the corresponding CS pin if configured as static output (see DATA1
register). For the CS pins configured as static inputs the corresponding CD0..3 will be
written by the values applied to those pins.
I/O data register channel #3 (data3)
Addr=08h; reset value=00h
Addr=09h; reset value=X0h
Used only if bit 4 of CONF register (STA)=0; dynamic I/O mode:
Table 20.
R/W
R/W
R/W
R/W
Bit7
Bit7
Bit7
Bit7
D2
D3
7
7
Dynamic I/O data register channel #2 (DATA2) bits
Dynamic I/O data register channel #2 (DATA2) bits
Static I/O data register channel #2 (DATA2) bits
Dynamic I/O data register channel #3 (data3) bits
Bit6
Bit6
Bit6
Bit6
D2
D3
0
0
0
0
6
6
Bit5
Bit5
Bit5
Bit5
D2
D3
0
0
0
0
5
5
Bit4
Bit4
Bit4
Bit4
D2
D3
0
0
0
0
4
4
D2
Bit3
Bit3
Bit3
CD
Bit3
D2
D3
0
0
0
1
11
3
3
3
D2
Bit2
Bit2
Bit2
CD
Bit2
D2
D3
1
1
1
0
10
2
2
2
Register description
Bit1
Bit1
Bit1
CD
Bit1
D2
D2
D3
1
1
1
0
1
9
1
1
Bit0
Bit0
Bit0
CD
Bit0
D2
D2
D3
0
1
0
0
25/64
0
8
0
0