STLC5048TR STMicroelectronics, STLC5048TR Datasheet - Page 19

• Manufacturer Part Number: STLC5048TR
• Description: IC CODEC/FILTER PROGR 4CH 64TQFP
• Manufacturer: STMicroelectronics
• Type: PCM Codec/Filterr

Specifications of STLC5048TR

• Data Interface: PCM Audio Interface
• Resolution (bits): 16 b
• Number Of Adcs / Dacs: 4 / 4
• Sigma Delta: Yes
• Voltage - Supply, Analog: 3.3 V ~ 5 V
• Voltage - Supply, Digital: 3.3 V ~ 5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STLC5048
4.10
period specified by means of T_OUT command, an internal time out rejects the instruction.
The time-out time is verified between two consecutive MCU interface access (between the
falling edge of the CS and the following rising edge).
This feature is used to verify the synchronization of the MCU interface: however it can be
disabled if not desired (see T_OUT register description). To check this synchronization is
provided a specific register (SYNCK) that returns always a predefined value: if the returned
value is different the MCU interface is in out of sync state (the device is waiting a data byte
while the MCU is writing an address or vice versa). In this case, it is possible to realign it by
means of the execution of a specific single byte instruction (REACOM) from 1 to 53 times,
depending on the instructions.
Every time an illegal operation (access to not allowed address, time-out violation or clock
pulse different than 8 inside a CS active) is performed the MCU interface is put on an error
state: to resume it from this state a single REACOM instruction can be used.
Anyway after a REACOM instruction a successful SYNC instruction guarantees the correct
synchronization.
One additional wire provided to the control interface is an open drain interrupt output (INT)
that goes low when a change of status is detected on the I/O pins or other interrupt source
are active (see
of the register corresponding the cause that has generated the interrupt (see INT register
description).
A particular register (COMEN) allows to enable a command on different channel at the
same time. Every time a command operation is performed at least one channel must be
enabled in this register.
This feature is useful when all channels must be configured in the same condition. When a
command is used to perform a read operation only one channel can be enabled at the same
time.
To check the configuration of the device a checksum value is provided. This value is
calculated on all coefficient parameters entered (coefficients of KD, AFE_CFF, GRX, GTX,
RFC, XFC, BFC, ZFC blocks; see the CKSUM register description). Two commands are
required to get this value: the first one (CKSTART) starts the internal checksum calculation,
the second one (CKSUM) returns the calculated value. Between this two commands no
other operation are allowed. The checksum value is available within 400us the CKSTART
command.
Coefficient checksum is defined by the following algorithm:
This algorithm guarantees a fault coverage of 1 - 2
Programming the device
After the power up, the filters and gain blocks can be programmed also with all the channels
set in power down. in this case the PDR bit of the COMEN register must be set to 0.
With the proper setting of the COMEN register, the commands can be applied to more than
one channel at the same time.
To read the coefficient values loaded in the RAM, only one channel per time must be
enabled in the COMEN register.
Section 5.7: Interrupt register (INT)
). INT is automatically reset after reading
-16
.
X
16
+
X
12
Functional description
+
X
5
+
1
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