CY7C67200-48BAXI Cypress Semiconductor Corp, CY7C67200-48BAXI Datasheet - Page 31

• Manufacturer Part Number: CY7C67200-48BAXI
• Description: USB HOST/PERIPH CNTRLR 48LFBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-OTG™r
• Type: OTG Programmable USB On The Gor

Specifications of CY7C67200-48BAXI

• Package / Case: 48-LFBGA
• Controller Type: USB Peripheral Controller
• Interface: Serial
• Voltage - Supply: 2.7 V ~ 3.6 V, 3 V ~ 3.6 V
• Current - Supply: 80mA, 135mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Data Rate: 2 Mbps
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Operating Supply Voltage: 2.7 V to 3.6 V
• Controller Family/series: PSoC 1
• Core Size: 16 Bit
• No. Of I/o's: 25
• Program Memory Size: 16KB
• Ram Memory Size: 8KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2262; CY7C67200-48BAXI

Document #: 38-08014 Rev. *G
Register Description
The Device n Endpoint n Count register designates the maximum packet size that can be received from the host for OUT transfers
for a single endpoint. This register also designates the packet size to be sent to the host in response to the next IN token for a
single endpoint. The maximum packet length is 1023 bytes in ISO mode. There are a total of eight endpoints for each of the two
ports. All endpoints have the same definition for their Device n Endpoint n Count register.
Count (Bits [9:0])
The Count field sets the current transaction packet length for a single endpoint.
Reserved
All reserved bits must be written as ‘0’.
Device n Endpoint n Status Register [R/W]
Register Description
The Device n Endpoint n Status register provides packet status
information for the last transaction received or transmitted.
This register is updated in hardware and does not need to be
cleared by firmware. There are a total of eight endpoints for
each of the two ports. All endpoints have the same definition
for their Device n Endpoint n Status register.
The Device n Endpoint n Status register is a memory-based
register that must be initialized to 0x0000 before USB Device
operations are initiated. After initialization, this register must
not be written to again.
Overflow Flag (Bit 11)
The Overflow Flag bit indicates that the received data in the
last data transaction exceeded the maximum length specified
in the Device n Endpoint n Count register. The Overflow Flag
should be checked in response to a Length Exception signified
by the Length Exception Flag set to ‘1’.
1: Overflow condition occurred
0: Overflow condition did not occur
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
• Device n Endpoint 0 Status Register [Device 1: 0x0206 Device 2: 0x0286]
• Device n Endpoint 1 Status Register [Device 1: 0x0216 Device 2: 0x0296]
• Device n Endpoint 2 Status Register [Device 1: 0x0226 Device 2: 0x02A6]
• Device n Endpoint 3 Status Register [Device 1: 0x0236 Device 2: 0x02B6]
• Device n Endpoint 4 Status Register [Device 1: 0x0246 Device 2: 0x02C6]
• Device n Endpoint 5 Status Register [Device 1: 0x0256 Device 2: 0x02D6]
• Device n Endpoint 6 Status Register [Device 1: 0x0266 Device 2: 0x02E6]
• Device n Endpoint 7 Status Register [Device 1: 0x0276 Device 2: 0x02F6]
Stall
Flag
R/W
15
X
-
X
7
14
X
NAK
-
Flag
R/W
6
X
Reserved
Figure 33. Device n Endpoint n Status Register
Exception Flag
13
X
-
Length
R/W
X
5
12
X
-
Setup
Flag
R/W
4
X
Underflow Flag (Bit 10)
The Underflow Flag bit indicates that the received data in the
last data transaction was less then the maximum length
specified in the Device n Endpoint n Count register. The
Underflow Flag should be checked in response to a Length
Exception signified by the Length Exception Flag set to ‘1’.
1: Underflow condition occurred
0: Underflow condition did not occur
OUT Exception Flag (Bit 9)
The OUT Exception Flag bit indicates when the device
received an OUT packet when armed for an IN.
1: Received OUT when armed for IN
0: Received IN when armed for IN
Overflow
Flag
R/W
11
X
Sequence
Flag
R/W
3
X
Underflow
Flag
R/W
10
X
Timeout
Flag
R/W
X
2
Exception Flag
OUT
R/W
X
9
Error
Flag
R/W
X
1
CY7C67200
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Exception Flag
R/W
IN
ACK
Flag
R/W
X
8
X
0
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