CY7C67200-48BAXI Cypress Semiconductor Corp, CY7C67200-48BAXI Datasheet - Page 44

• Manufacturer Part Number: CY7C67200-48BAXI
• Description: USB HOST/PERIPH CNTRLR 48LFBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-OTG™r
• Type: OTG Programmable USB On The Gor

Specifications of CY7C67200-48BAXI

• Package / Case: 48-LFBGA
• Controller Type: USB Peripheral Controller
• Interface: Serial
• Voltage - Supply: 2.7 V ~ 3.6 V, 3 V ~ 3.6 V
• Current - Supply: 80mA, 135mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Data Rate: 2 Mbps
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Operating Supply Voltage: 2.7 V to 3.6 V
• Controller Family/series: PSoC 1
• Core Size: 16 Bit
• No. Of I/o's: 25
• Program Memory Size: 16KB
• Ram Memory Size: 8KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2262; CY7C67200-48BAXI

Document #: 38-08014 Rev. *G
HSS Control Register [0xC070] [R/W]
Register Description
The HSS Control register provides high-level status and
control over the HSS port.
HSS Enable (Bit 15)
The HSS Enable bit enables or disables HSS operation.
1: Enables HSS operation
0: Disables HSS operation
RTS Polarity Select (Bit 14)
The RTS Polarity Select bit selects the polarity of RTS.
1: RTS is true when LOW
0: RTS is true when HIGH
CTS Polarity Select (Bit 13)
The CTS Polarity Select bit selects the polarity of CTS.
1: CTS is true when LOW
0: CTS is true when HIGH
XOFF (Bit 12)
The XOFF bit is a read-only bit that indicates if an XOFF has
been received. This bit is automatically cleared when an XON
is received.
1: XOFF received
0: XON received
XOFF Enable (Bit 11)
The XOFF Enable bit enables or disables XON/XOFF software
handshaking.
1: Enable XON/XOFF software handshaking
0: Disable XON/XOFF software handshaking
CTS Enable (Bit 10)
The CTS Enable bit enables or disables CTS/RTS hardware
handshaking.
1: Enable CTS/RTS hardware handshaking
0: Disable CTS/RTS hardware handshaking
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Done Interrupt
Transmit
Enable
Enable
HSS
R/W
R/W
15
0
7
0
Polarity Select
Done Interrupt
Receive
Enable
RTS
R/W
R/W
14
0
6
0
Polarity Select
Stop Bit
Figure 48. HSS Control Register
One
R/W
CTS
R/W
5
0
13
0
Transmit
Ready
XOFF
R
4
0
12
R
0
Receive Interrupt Enable (Bit 9)
The Receive Interrupt Enable bit enables or disables the
Receive Ready and Receive Packet Ready interrupts.
1: Enable the Receive Ready and Receive Packet Ready
interrupts
0: Disable the Receive Ready and Receive Packet Ready
interrupts
Done Interrupt Enable (Bit 8)
The Done Interrupt Enable bit enables or disables the Transmit
Done and Receive Done interrupts.
1: Enable the Transmit Done and Receive Done interrupts
0: Disable the Transmit Done and Receive Done interrupts
Transmit Done Interrupt Flag (Bit 7)
The Transmit Done Interrupt Flag bit indicates the status of the
Transmit Done Interrupt. It will set when a block transmit is
finished. To clear the interrupt, a ‘1’ must be written to this bit.
1: Interrupt triggered
0: Interrupt did not trigger
Receive Done Interrupt Flag (Bit 6)
The Receive Done Interrupt Flag bit indicates the status of the
Receive Done Interrupt. It will set when a block transmit is
finished. To clear the interrupt, a ‘1’ must be written to this bit.
1: Interrupt triggered
0: Interrupt did not trigger
One Stop Bit (Bit 5)
The One Stop Bit bit selects between one and two stop bits for
transmit byte mode. In receive mode, the number of stop bits
may vary and does not need to be fixed.
1: One stop bit
0: Two stop bits
Packet
Select
Mode
Enable
R/W
XOFF
R/W
3
0
11
0
Overflow
Receive
Enable
Flag
R/W
CTS
R/W
2
0
10
0
Packet Ready
Receive
Interrupt
Receive
Enable
Flag
R/W
R
1
0
9
0
CY7C67200
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Interrupt
Receive
Enable
Ready
Done
R/W
Flag
R
8
0
0
0
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