CY7C67200-48BAXI Cypress Semiconductor Corp, CY7C67200-48BAXI Datasheet - Page 51

USB HOST/PERIPH CNTRLR 48LFBGA

CY7C67200-48BAXI

Manufacturer Part Number
CY7C67200-48BAXI
Description
USB HOST/PERIPH CNTRLR 48LFBGA
Manufacturer
Cypress Semiconductor Corp
Series
EZ-OTG™r
Type
OTG Programmable USB On The Gor
Datasheet

Specifications of CY7C67200-48BAXI

Package / Case
48-LFBGA
Controller Type
USB Peripheral Controller
Interface
Serial
Voltage - Supply
2.7 V ~ 3.6 V, 3 V ~ 3.6 V
Current - Supply
80mA, 135mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Data Rate
2 Mbps
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 85 C
Supply Current
80 mA
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Operating Supply Voltage
2.7 V to 3.6 V
Controller Family/series
PSoC 1
Core Size
16 Bit
No. Of I/o's
25
Program Memory Size
16KB
Ram Memory Size
8KB
Cpu Speed
48MHz
No. Of Timers
2
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
CY3663 - KIT DEV EZ-OTG/EZ-HOST
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
428-2262
CY7C67200-48BAXI

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Document #: 38-08014 Rev. *G
SIEXmsg Register [W]
Register Description
The SIEXmsg register allows an interrupt to be generated on the HPI port. Any write to this register causes the SIEXmsg flag in
the HPI Status Port to go high and also causes an interrupt on the HPI_INTR pin. The SIEXmsg flag is automatically cleared
when the HPI port reads from this register.
Data (Bits [15:0])
The Data field[15:0] simply must have any value written to it to cause SIExmsg flag in the HPI Status Port to go high.
HPI Mailbox Register [0xC0C6] [R/W]
Register Description
The HPI Mailbox register provides a common mailbox between the CY7C67200 and the external host processor.
If enabled, the HPI Mailbox RX Full interrupt triggers when the external host processor writes to this register. When the
CY7C67200 reads this register the HPI Mailbox RX Full interrupt automatically gets cleared.
If enabled, the HPI Mailbox TX Empty interrupt triggers when the external host processor reads from this register. The HPI Mailbox
TX Empty interrupt is automatically cleared when the CY7C67200 writes to this register.
In addition, when the CY7C67200 writes to this register, the HPI_INTR signal on the HPI port asserts signaling the external
processor that there is data in the mailbox to read. The HPI_INTR signal deasserts when the external host processor reads from
this register.
Message (Bits [15:0])
The Message field contains the message that the host processor wrote to the HPI Mailbox register.
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
• SIE1msg Register 0x0144
• SIE2msg Register 0x0148
R/W
R/W
15
15
W
W
X
X
7
0
7
0
R/W
R/W
14
14
W
W
X
X
6
0
6
0
Figure 59. HPI Mailbox Register
R/W
R/W
Figure 58. SIEXmsg Register
13
13
W
W
X
X
5
0
5
0
R/W
R/W
12
12
W
W
X
X
4
0
4
0
Message...
...Message
Data...
...Data
R/W
R/W
11
W
W
11
X
X
3
0
3
0
R/W
R/W
10
10
W
W
X
X
2
0
2
0
R/W
R/W
W
W
X
X
1
0
9
1
9
0
CY7C67200
Page 51 of 78
R/W
R/W
W
W
X
X
0
0
8
0
8
0
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