CY7C67200-48BAXI Cypress Semiconductor Corp, CY7C67200-48BAXI Datasheet - Page 49

• Manufacturer Part Number: CY7C67200-48BAXI
• Description: USB HOST/PERIPH CNTRLR 48LFBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-OTG™r
• Type: OTG Programmable USB On The Gor

Specifications of CY7C67200-48BAXI

• Package / Case: 48-LFBGA
• Controller Type: USB Peripheral Controller
• Interface: Serial
• Voltage - Supply: 2.7 V ~ 3.6 V, 3 V ~ 3.6 V
• Current - Supply: 80mA, 135mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Data Rate: 2 Mbps
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Operating Supply Voltage: 2.7 V to 3.6 V
• Controller Family/series: PSoC 1
• Core Size: 16 Bit
• No. Of I/o's: 25
• Program Memory Size: 16KB
• Ram Memory Size: 8KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2262; CY7C67200-48BAXI

Document #: 38-08014 Rev. *G
HPI Breakpoint Register [0x0140] [R]
Register Description
The HPI Breakpoint register is a special on-chip memory location, which the external processor can access using normal HPI
memory read/write cycles. This register is read-only by the CPU but is read/write by the HPI port. The contents of this register
have the same effect as the Breakpoint register [0xC014]. This special Breakpoint register is used by software debuggers which
interface through the HPI port instead of the serial port.
When the program counter matches the Breakpoint Address, the INT127 interrupt triggers. To clear this interrupt, a zero value
must be written to this register.
Address (Bits [15:0])
The Address field is a 16-bit field containing the breakpoint address.
Interrupt Routing Register [0x0142] [R]
Register Description
The Interrupt Routing register allows the HPI port to take over
some or all of the SIE interrupts that usually go to the on-chip
CPU. This register is read-only by the CPU but is read/write by
the HPI port. By setting the appropriate bit to ‘1’, the SIE
interrupt is routed to the HPI port to become the HPI_INTR
signal and also readable in the HPI Status register. The bits in
this register select where the interrupts are routed. The
individual interrupt enable is handled in the SIE interrupt
enable register.
VBUS to HPI Enable (Bit 15)
The VBUS to HPI Enable bit routes the OTG VBUS interrupt
to the HPI port instead of the on-chip CPU.
1: Route signal to HPI port
0: Do not route signal to HPI port
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
VBUS to HPI
Resume2 to
HPI Enable
Enable
15
15
R
R
R
0
7
0
0
7
0
-
Resume1 to
HPI Enable
ID to HPI
Enable
14
14
R
0
R
R
6
0
0
6
0
-
SOF/EOP2 to
Figure 57. Interrupt Routing Register
HPI Enable
Figure 56. HPI Breakpoint Register
13
13
R
0
R
R
5
0
0
5
0
-
Reserved
SOF/EOP2 to
CPU Enable
12
12
R
0
R
R
4
0
4
0
1
-
ID to HPI Enable (Bit 14)
The ID to HPI Enable bit routes the OTG ID interrupt to the HPI
port instead of the on-chip CPU.
1: Route signal to HPI port
0: Do not route signal to HPI port
SOF/EOP2 to HPI Enable (Bit 13)
The SOF/EOP2 to HPI Enable bit routes the SOF/EOP2
interrupt to the HPI port.
1: Route signal to HPI port
0: Do not route signal to HPI port
Address...
...Address
SOF/EOP1 to
Done2 to HPI
HPI Enable
Enable
11
11
R
0
R
R
3
0
3
0
0
-
SOF/EOP1 to
Done1 to HPI
CPU Enable
Enable
10
10
R
0
R
R
2
0
2
0
1
-
Reset1 to HPI
Reset2 to HPI
Enable
Enable
R
9
0
R
R
1
0
1
0
9
0
-
CY7C67200
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HPI Swap 1
HPI Swap 0
Enable
Enable
R
8
0
R
R
0
0
0
0
8
0
-
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