CY7C67200-48BAXI Cypress Semiconductor Corp, CY7C67200-48BAXI Datasheet - Page 57

• Manufacturer Part Number: CY7C67200-48BAXI
• Description: USB HOST/PERIPH CNTRLR 48LFBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-OTG™r
• Type: OTG Programmable USB On The Gor

Specifications of CY7C67200-48BAXI

• Package / Case: 48-LFBGA
• Controller Type: USB Peripheral Controller
• Interface: Serial
• Voltage - Supply: 2.7 V ~ 3.6 V, 3 V ~ 3.6 V
• Current - Supply: 80mA, 135mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Data Rate: 2 Mbps
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Operating Supply Voltage: 2.7 V to 3.6 V
• Controller Family/series: PSoC 1
• Core Size: 16 Bit
• No. Of I/o's: 25
• Program Memory Size: 16KB
• Ram Memory Size: 8KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2262; CY7C67200-48BAXI

Document #: 38-08014 Rev. *G
Transmit Interrupt Flag (Bit 1)
The Transmit Interrupt Flag is a read only bit that indicates a
byte mode transmit interrupt has triggered.
1: Indicates a byte mode transmit interrupt has triggered
0: Indicates a byte mode transmit interrupt has not triggered
SPI Interrupt Clear Register [0xC0D0] [W]
Register Description
The SPI Interrupt Clear register is a write-only register that
allows the SPI Transmit and SPI Transfer Interrupts to be
cleared.
Transmit Interrupt Clear (Bit 1)
The Transmit Interrupt Clear bit is a write-only bit that clears
the byte mode transmit interrupt. This bit is self-clearing.
1: Clear the byte mode transmit interrupt
0: No function
SPI CRC Control Register [0xC0D2] [R/W]
Register Description
The SPI CRC Control register provides control over the CRC
source and polynomial value.
CRC Mode (Bits [15:14)
The CRCMode field selects the CRC polynomial as defined in
Table
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
35.
R/W
15
15
0
0
7
0
-
-
7
0
-
CRC Mode
R/W
14
14
0
0
6
0
-
-
6
0
-
Figure 65. SPI Interrupt Clear Register
Figure 66. SPI CRC Control Register
Enable
CRC
R/W
13
13
0
0
5
0
-
-
5
0
-
Reserved
Clear
CRC
R/W
12
12
4
0
0
4
0
0
-
-
-
...Reserved
Transfer Interrupt Flag (Bit 0)
The Transfer Interrupt Flag is a read only bit that indicates a
block mode interrupt has triggered.
1: Indicates a block mode interrupt has triggered
0: Indicates a block mode interrupt has not triggered
Transfer Interrupt Clear (Bit 0)
The Transfer Interrupt Clear bit is a write-only bit that will clear
the block mode interrupt. This bit is self clearing.
1: Clear the block mode interrupt
0: No function
Reserved
All reserved bits must be written as ‘0’.
Table 35.CRC Mode Definition
Reserved
CRCMode
[9:8]
00
01
10
11
Receive
CRC
R/W
11
11
3
0
-
3
0
0
0
-
-
MMC 16-bit: X^16 + X^12 + X^5 + 1
MST 16-bit: X^16+ X^15 + X^2 + 1
Reserved, 16-bit polynomial 1.
One in
CRC7 7-bit: X^7+ X^3 + 1
CRC
2
0
10
10
-
R
2
0
0
0
-
-
(CCITT Standard)
CRC Polynomial
Interrupt Clear
Transmit
Zero in
CRC
W
1
0
R
1
0
9
0
9
0
-
-
CY7C67200
Page 57 of 78
Interrupt Clear
Reserved...
Transfer
W
0
0
0
0
8
0
8
0
-
-
-
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