CY7C67200-48BAXI Cypress Semiconductor Corp, CY7C67200-48BAXI Datasheet - Page 41

• Manufacturer Part Number: CY7C67200-48BAXI
• Description: USB HOST/PERIPH CNTRLR 48LFBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-OTG™r
• Type: OTG Programmable USB On The Gor

Specifications of CY7C67200-48BAXI

• Package / Case: 48-LFBGA
• Controller Type: USB Peripheral Controller
• Interface: Serial
• Voltage - Supply: 2.7 V ~ 3.6 V, 3 V ~ 3.6 V
• Current - Supply: 80mA, 135mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Data Rate: 2 Mbps
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Operating Supply Voltage: 2.7 V to 3.6 V
• Controller Family/series: PSoC 1
• Core Size: 16 Bit
• No. Of I/o's: 25
• Program Memory Size: 16KB
• Ram Memory Size: 8KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2262; CY7C67200-48BAXI

Document #: 38-08014 Rev. *G
HSS Enable (Bit 7)
The HSS Enable bit routes HSS to GPIO[15:12].
1: HSS is routed to GPIO
0: HSS is not routed to GPIOs. GPIO[15:12] are free for other
purposes.
SPI Enable (Bit 5)
The SPI Enable bit routes SPI to GPIO[11:8]. If the SAS
Enable bit is set, it overrides and routes the SPI_nSSI pin to
GPIO15.
1: SPI is routed to GPIO[11:8]
0: SPI is not routed to GPIO[11:8]. GPIO[11:8] are free for
other purposes.
GPIO 0 Output Data Register [0xC01E] [R/W]
Register Description
The GPIO 0 Output Data register controls the output data of the GPIO pins. The GPIO 0 Output Data register controls GPIO15
to GPIO0 while the GPIO 1 Output Data register controls GPIO31 to GPIO19. When read, this register reads back the last data
written, not the data on pins configured as inputs (see Input Data Register).
Writing a 1 to any bit will output a high voltage on the corresponding GPIO pin.
Reserved
All reserved bits must be written as ‘0’.
GPIO 1 Output Data Register [0xC024] [R/W]
Register Description
The GPIO 1 Output Data register controls the output data of the GPIO pins. The GPIO 0 Output Data register controls GPIO15
to GPIO0 while the GPIO 1 Output Data register controls GPIO31 to GPIO19. When read, this register reads back the last data
written, not the data on pins configured as inputs (see Input Data Register).
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
GPIO15
GPIO31
GPIO23
GPIO7
R/W
R/W
R/W
R/W
15
15
0
7
0
0
7
0
GPIO14
GPIO30
GPIO22
GPIO6
R/W
R/W
R/W
R/W
14
14
0
6
0
0
6
0
Figure 42. GPIO 0 Output Data Register
Figure 43. GPIO n Output Data Register
GPIO13
GPIO29
GPIO21
GPIO5
R/W
R/W
R/W
R/W
13
13
0
5
0
0
5
0
GPIO12
GPIO20
GPIO4
R/W
R/W
R/W
12
12
0
4
0
0
4
0
-
Interrupt 0 Polarity Select (Bit 1)
The Interrupt 0 Polarity Select bit selects the polarity for IRQ0.
1: Sets IRQ0 to rising edge
0: Sets IRQ0 to falling edge
Interrupt 0 Enable (Bit 0)
The Interrupt 0 Enable bit enables or disables IRQ0. The GPIO
bit on the interrupt Enable register must also be set in order for
this for this interrupt to be enabled.
1: Enable IRQ0
0: Disable IRQ0
Reserved
All reserved bits must be written as ‘0’.
GPIO11
GPIO19
GPIO3
R/W
R/W
R/W
11
11
0
3
0
0
3
0
-
Reserved
GPIO10
GPIO2
R/W
R/W
10
10
0
2
0
0
2
0
-
-
Reserved
GPIO9
GPIO1
R/W
R/W
9
0
1
0
9
0
-
1
0
-
CY7C67200
Page 41 of 78
GPIO24
GPIO8
GPIO0
R/W
R/W
R/W
8
0
0
0
8
0
0
0
-
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