FDC37C665GT-MS SMSC, FDC37C665GT-MS Datasheet - Page 12

• Manufacturer Part Number: FDC37C665GT-MS
• Description: IC CTRLR SUPER I/O MULTI 100-QFP
• Manufacturer: SMSC

Specifications of FDC37C665GT-MS

• Controller Type: I/O Controller
• Interface: ISA Host
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 35mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1007

PIN NO.
82,92
80,90
85,87
nClear to Send
nData Set Ready nDSR1,
nData Carrier
Detect
NAME
DESCRIPTION OF PIN FUNCTIONS
nCTS1,
nCTS2
nDSR2
nDCD1,
nDCD2
SYMBOL
BUFFER
TYPE
I
I
I
12
Active low Clear to Send inputs for primary
and secondary serial ports.
signal which notifies the UART that the
modem is ready to receive data. The CPU
can monitor the status of nCTS signal by
reading bit 4 of Modem Status Register
(MSR). A nCTS signal state change from
low to high after the last MSR read will set
MSR bit 0 to a 1. If bit 3 of Interrupt Enable
Register is set, the interrupt is generated
when nCTS changes state.
signal has no effect on the transmitter.
Note: Bit 4 of MSR is the complement of
nCTS.
Active low Data Set Ready inputs for
primary and secondary serial ports.
Handshake signal which notifies the UART
that the modem is ready to establish the
communication link. The CPU can monitor
the status of nDSR signal by reading bit 5 of
Modem Status Register (MSR).
signal state change from low to high after
the last MSR read will set MSR bit 1 to a 1.
If bit 3 of Interrupt Enable Register is set,
the interrupt is generated when nDSR
changes state. Note: Bit 5 of MSR is the
complement of nDSR.
Active low Data Carrier Detect inputs for
primary and secondary serial ports.
Handshake signal which notifies the UART
that carrier signal is detected by the
modem. The CPU can monitor the status of
nDCD signal by reading bit 7 of Modem
Status Register (MSR).
state change from low to high after the last
MSR read will set MSR bit 3 to a 1. If bit 3
of Interrupt Enable Register is set, the
interrupt is generated when nDCD changes
state.
complement of nDCD.
Note:
DESCRIPTION
Bit 7 of MSR is the
A nDCD signal
Handshake
The nCTS
A nDSR