FDC37C665GT-MS SMSC, FDC37C665GT-MS Datasheet - Page 147

• Manufacturer Part Number: FDC37C665GT-MS
• Description: IC CTRLR SUPER I/O MULTI 100-QFP
• Manufacturer: SMSC

Specifications of FDC37C665GT-MS

• Controller Type: I/O Controller
• Interface: ISA Host
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 35mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1007

Parallel Port FIFO (Mode 101)
The standard parallel port is run at or near the
peak 500Kbytes/sec allowed in the forward
direction using DMA. The state machine does
not examine nAck and begins the next transfer
based on Busy. Refer to Figure 17.
ECP Parallel Port Timing
The timing is designed to allow operation at
approximately 2.0Mbytes/sec over a 15ft cable.
If a shorter cable is used then the bandwidth will
increase.
Forward-Idle
When the host has no data to send it keeps
HostClk (nStrobe) high and the peripheral will
leave PeriphClk (Busy) low.
Forward Data Transfer Phase
The interface transfers data and commands
from the host to the peripheral using an
interlocked
peripheral may indicate its desire to send data
to the host by asserting nPeriphRequest.
The Forward Data Transfer Phase may be
entered from the Forward-Idle Phase. While in
the
asynchronously
(nFault) to request that the channel be reversed.
PeriphAck (Busy) low. The host then sets
HostClk (nStrobe) low when it is prepared to
send data. The data must be stable for the
specified setup time prior to the falling edge of
HostClk. The peripheral then sets PeriphAck
(Busy) high to acknowledge the handshake. The
host then sets HostClk (nStrobe) high. The
peripheral then accepts the data and sets
When the peripheral is not busy it sets
Forward
PeriphAck
Phase
assert
the
and
the
peripheral
nPeriphRequest
ECP PARALLEL PORT TIMING
HostClk.
may
The
147
PeriphAck (Busy) low, completing the transfer.
This sequence is shown in Figure 18.
The timing is designed to provide 3 cable
round-trip times for data setup if Data is driven
simultaneously with HostClk (nStrobe).
Reverse-Idle Phase
The peripheral has no data to send and keeps
PeriphClk high. The host is idle and keeps
HostAck low.
Reverse Data Transfer Phase
The interface transfers data and commands
from the peripheral to the host using an
interlocked HostAck and PeriphClk.
The Reverse Data Transfer Phase may be
entered from the Reverse-Idle Phase. After the
previous byte has beed accepted the host sets
HostAck (nAutoFd) low. The peripheral then sets
PeriphClk (nAck) low when it has data to send.
The data must be stable for the specified setup
time prior to the falling edge of PeriphClk. When
the host is ready it to accept a byte it sets.
HostAck (nAutoFd) high to acknowledge the
handshake. The peripheral then sets PeriphClk
(nAck) high. After the host has accepted the
data it sets HostAck (nAutoFd) low, completing
the transfer. This sequence is shown in Figure
19.
Output Drivers
To facilitate higher performance data transfer,
the use of balanced CMOS active drivers for
critical
PeriphAck, PeriphClk) are used ECP Mode.
Because the use of active drivers can present
compatibility problems in Compatible Mode (the
control signals, by tradition, are specified as
signals
(Data,
HostAck,
HostClk,